Research And Design Of IPSec Cryptographic Coprocessor

Software-based implementation of the IPSec Protocol can be very sophisticated, and it will take a lot of time to perform complicated cryptological algorithms. These result in the performance problem.A highly efficient IPSec cryptographic processor is proposed in this dissertation, which consists of a 32-bit RISC processor block using instruction extended technique for RSA, ECC public key crypto algorithms and coprocessor blocks dedicated to the AES private key crypto algorithm.Unlike previous implements of AES which rely on look-up tables to implement the SubBytes, we use the combinational logic which is only based on arithmeticoperations in the finite field GF(2~8) with 3 substages. We also propose the 3-in-l keygenerator to cooperate with the AES block. All the round keys are generated on the fly without additional memory to srore the sub-keys. Using the proposed architecture, a fully subpipelined AES-128 unit can achieve a throughput of 12 Gbps on an Altera EP20KE device in non-feedback mode. The performances of RSA, ECC dependessentially on efficient arithmetic in the underlying finite field GF(p) and GF{(2~m).We outline that multiplication of binary polynomials can be easily integrated into a multiplier datapath for integers without significant additional hardware based on duel-field multiplier for MULGF2 instruction. We also analyze different algorithms for modular arithmetic in processor equipped with fast MAC unit. Our analysis show that the small architectural enhancements can dramatically speed up the arithmetic operations.