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Design And Implementation Of A Full-Speed USB Device Controller Interface IP-core

Posted on:2006-05-22Degree:MasterType:Thesis
Country:ChinaCandidate:W H HuangFull Text:PDF
GTID:2178360182469177Subject:Pattern Recognition and Intelligent Systems
Abstract/Summary:PDF Full Text Request
USB technique was developed to resolve the defects of traditional PC's peripheral component interface such as various formats, low speed, boring installation to operating system etc, at the beginning. It has such virtues as hi-speed, bi-direction, low cost and plug and play etc. The application of USB has becoming more and more popular since Microsoft's operating system—Win98 announced its kernel supports for USB. Based on analysis of USB1.1 and USB2.0 Spec, especially on the Spec's protocol layer, this paper arrives at a scheme to implement full-speed USB device controller. With the method of divide-and-conqure and flow of Top-Down, the device controller's digital logic circuits are realized by Verilog HDL. Digital logic part is mainly made up of such modules as SIE, MAI, and EPCTL etc. SIE, which is the core logics of the device controller, has 4 sub-modules: GECLK, EVENTCTL, PHY and MAC, and implements such functions as clock extraction, bus status detection, data flow's NRZI coding and decoding, generation and verification of CRC codes, conversion of serial to parallel and parallel to serial, etc. EPCTL controls the 3 pairs of endpoints of the device controller's writing and reading operations. MAI, which manages all the control status registers, exchange data with MCU through 8-bit data bus. A FPGA verification platform was built to verify the functionality of the IP Core. Then using the 0.25um standard technology library, the Cell-Based semi-custom ASIC backend design of this IP-core is finished. Post functional simulations and physical verifications about the layout such as DRC, LVS are carried out, and the final layout with a transceiver integrated together is taped out.
Keywords/Search Tags:USB Spec, IP Core, FPGA verification, semi-custom ASIC, physical verification
PDF Full Text Request
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