Study And Implementation The Verification Methodology Of Smart Card IC Based FPGA

With the development of IC design technology and the increasing of the circuit density, the verification has become the main bottleneck in design process. Existing EDA verification software could not reach to satisfying coverage when deals with large scale designs or SoC. But by virtue of its performance of speed, easy to modify and real time, FPGA verification has been an important way in IC design.In smart card area, with the popularization of the smart card in all fields, application requests much safer, more reliable and multiple functional smart card. In order to increase smart card chip verification coverage and to shorten the time of market, this thesis made some theory analysis and design practice for smart card verification based FPGA, including FPGA prototype platform design and verification method and implementation based the platform.Prototype platform design should be done first in FPGA verification. We made requirement analysis according to smart card principle and current market status. Functional and performance definitions about the FPGA prototype platform were made according to the relative theory. What's more, we discussed the principle of FPGA selection, analog circuit design and digital design difference based FPGA.The verification methodology based FPGA prototype platform is the key to make sure that the chip design is correct. We put forward some new method to verify the chip function, according to smart card protocol, verification theory, FPGA and test equipment performance. Furthermore, it discussed the verification method principle, implementation and debugging method in detail, and summarized a whole flow of FPGA verification which will apply to the verification project of the actual chip.The successful verification of this smart card chip, is not only the evidence to the FPGA verification theory, but also has a creative signification on other chips. With this FPGA verification method, it can increase verification efficiency and ensure chip correct design to aim to reduce the chip cost and shorten the time of market.