Simulation Of Cache On Chip Multiprocessor

Along with the popularization of chip multiprocessor (CMP) and the development on integrated circuit manufacturing, the design of memory system is facing unprecedented pressure. How to support the concurrent memory access from multiple processor better and more effectively reducing nanometer chip's wire delay and power consumption are the main problem to be solved for the on-chip cache system.These problems for cache system may also be new challenges to architecture simulation which is an important part of the processor designing. Unfortunately, most existing architecture simulators lack enough analysis and efficient performance simulation to the chip multiprocessor's cache and can not support intensive dynamic simulation on latency and power consumption of cache. To solve these problems, the paper focuses on the research of simulation to the cache of chip multiprocessor, and designed a performance model and a multi-metrics model respectively.Performance model can support an architecture-level performance simulation on cache system for FT 1000 multi-core processor. Compared to traditional single-core superscalar processor, cache on multi-core processor is greatly increased on size and complexity, which makes the performance model have to include many modules like cache module, cache control module, and coherence protocol, etc. Design ideas like deetailed and realistic reflecting the behavioral characteristics of the cache, using efficient data structures and algorithms, modular design and providing scalability are fully respected and utilized. In order to verify the correctness and availability of the model, some simulation experiments which use the SPEC 2000 benchmark have been presented. The result of the experiments also shows the advantages of architecture simulation technology itself, which is more convenient and fast presenting the different performance of target sysytem by different structural parameters.In recent years, many studies show that the optimization to chip area, delay and power consumption on micro-architectural level has more explore space than circuit-level. Based on this, beside the performance model, by referencing the design methods of CACTI and Wattch model, a multi-metrics model of cache was greated. As an open platform a model between underlying circuit and architecture level, multi-metrics model can fast and efficiently estimate cache area, latency and power consumption based on different feature size and structural parameters. Further with the performance model, multi-metrics model can realistically simulate cache latency, power consumption dynamically.Preliminary studies have shown that the cache performance model and multi-metrics model described in the paper can provide efficient simulation to CMP architecture on-chip caches, and it will play an important role in the relevant field of scientific research and engineering.