The Research And Realization Of Configurable AES Algorithm IP Core

ABSTRACT:With the rapid development of information technology, it is widely recognized that security issues will play more and more crucial roles in the future information systems. Cryptography as a sort of power weapon is widely used in the field of information security. So research on it becomes even more important and exigent. The thesis presents a configurable AES algorithm IP core with the reuse methodology. Compared to traditional method, this design provides higher speed, more physical security and wider range of applications.Firstly, the paper introduces the reuse methodology which is based on the reuse and design of IP core. Secondly, some mathematics knowledge for learning AES algorithm is introduced. And the AES algorithm is described in this paper, including its encryption, decryption, key expansion and operation mode. Then the hardware design is carried through. The AES module had been divided into three parts:the top module, the encryption and decryption module, and the key expansion module. The design of AES algorithm is implemented by using the hardware design language Verilog HDL. Through using the look-up table, the problem that some complicated mathematics operation takes negative affect on the speed of IP core has been resolved. The configurable structure also has been used so that the IP core can support 128,192 and 256 bits key.Besides simulation and verification, the IP core is also integrated into SoPC. These works have proved the design of IP core to meet the expected. And it reaches the requirement of reuse methodology.