VLSI Research And Implementation For Motion Compensation Process In H.264 Decoding System

H.264/AVC is the latest video compression standard developed by ISO and ITU-T. It outperformed the existing standards by at least two times through a series of new compression techniques. However, the excellent compression performance is attended by the huge computation complexity, which is a great challenge for the decoding system's hardware implementation. During the real-time decoding process, motion compensation process accounts for about 80% of the all the time needed. H.264 supports 1/4 sub-pixel interpolation operation using six-tap filters and up to 16 reference pictures, which make the reference block locating process and sub-pixel interpolation process the most complex and time-consuming parts in the decoding system. Therefore, improving the performance of motion compensation process plays a key role in improving the whole decoding system's performance. The main research topics and innovation points include:1. This paper proposes an efficient four-level hierarchical memory architecture which can reduce the external memory bandwidth greatly and can efficiently solve the excessive external memory access problem.2. This paper proposes a two-level pipeline architecture for sub-pixel interpolation. The first-level pipeline is utilized to explore the parallelism for the interpolation processes of different 4x4 blocks with two stages of fetching 4x4 block's reference pixels and interpolation computation operation. The second level pipeline scheme is used to accelerate sub-pixel interpolation computation operations of different pixels taking advantage of the independence of adjacent half-pixels and the symmetry between horizontal and vertical interpolation computation processes.3. This paper proposes an efficient reference picture management scheme. By establishing direct mapping between refidx and dpbidx and optimizing the process to locate reference picture, the implementation complexity of both motion compensation process'software and hardware parts is reduced.