An Efficient Multi-standard Motion Compensation Architecture Design For Video Coding

By incorporating the latest advancement in video coding technology,HEVC (High Efficiency Video Coding) achieves about50%bit rate reductionrelative to the previous H.264/AVC standard. The high compression ratiodelivered by HEVC makes it especially suitable for the next-generation videospecifications such as QFHD (Quad Full High Definition). In HEVC, MC (motioncompensation) interpolation is still one of the most computation intensivecomponents. New8-tap and4-tap interpolation filters are adopted in HEVCstandard, for luma and chroma components respectively, substitute the6-tapand bilinear filters in H.264/AVC. While the new filters contribute toimproved coding performance by delivering high-accuracy sub-pixelprediction, they also involve significantly increased complexity. Efficient VLSIarchitectures are therefore required for implementing the new algorithm.This paper firstly proposes an optimized HEVC MC interpolation architectureand then presents a multi-format MC interpolation architecture design basedon that.Firstly, this paper analyzed the new features of HEVC MC interpolationalgorithem. The area of the8-tap filers is reduced by applying the proposedreconfigurable architecture design. A pipeline structure optimized for thedata flow of HEVC interpolation is further proposed, in order to conceal thedata latency and shorn the critical path for improving the working frequencyand throughput. For parallelized interpolation engines, after discussing the workload of vertical filters, this paper also proposes a filter reuse scheme toreduce the cost for vertical filters. These proposals result in a total of34%area reduction. The implemented architecture supports a maximumthroughput of QFHD (3840x2160)@60fps at342MHz operating frequency,with a gate count of46.9k.Then, based on the proposed HEVC interpolator, this paper furtherpresents a multi-format architecture that incorporates the support forH.264/AVC and MPEG4. Firstly, a multi-mode filter is proposed for integratingthe3types of8-tap filter for HEVC, the6-tap filter for H.264/AVC and8-tapfilter for MPEG4. A reusable register array structure is proposed to effectivelysupport the data transferring and storage for different standards. Besides, acache-based bandwidth reduction scheme is proposed and the cache size isoptimized by applying interpolation re-ordering scheme.This paper uses Modelsim6.2and TSMC65nm technology forsimulation and synthesis, respectivelty. The implementation and experimentsresults show that the multi-format design achieves over23%area and80%bandwidth reduction in comparison with individual implementations, with agate count of51.0k.