A Parameterized Viterbi Decoder Based On FPGA

The Viterbi algorithm is used to find the most-likely state transition sequence in a state diagram ,and has been widely used in signal processing and digital communication.Specifically due to their forward error correction capability, the Viterbi decoder has often been used in digital communication system such as satellite communication systems, GSM,3G ,DVB and ATSC.In this paper, a parameterized Viterbi decoder based on FPGA is presented. The structure of the decoder, the realization of Verilog HDL and the simulation of the designed decoder are discussed deeply. These alterable parameters include generating polynomials, the number of ACS, the number of soft decision bits per symbol, traceback length and so on.The user can set the parameter which he needs. As the new in this paper ,a new memory organization, a new normalization method and a way of getting soft-decision bits helped by Matlab are presented.The designed soft-decision Viterbi decoder has been used in some satellite communication systems .