The Study And Implementation Of High-speed Viterbi Decoder

As the research of error-correct-coding theory developing deeply more and more, the applications of error-correcting codes have been used more widely. The convolutional codes, as the important one of error-correcting codes, are used by most communication systems in various situations. (2,1, 7) convolutional codes is a optimum code which has the short constraint length. It can be encoded or decoded easily. And this code has a good error-correcting performance.This paper study the theory and implementation of high-speed encoder and soft-decision Viterbi decoder of 3/4 punctured convolutional codes derived from (2,1,7) convolutional codes.Firstly, the new development of high-speed Viterbi decoding algorithms is introduced, and a new architecture for high-speed processing is proposed based on it. Then, we design the encoder and Viterbi decoder of (2, 1, 7) convolutional code by programming with VHDL language. The encoder and Viterbi decoder of high-speed 3/4 punctured codes are achieved base on the above designs. The programs have been configured into the Virtex-II series FPGA (XC2V2000-6bg575) of Xilinx Inc. Timing simulation and practical test indicates the speed of a single decoder of 3/4 punctured convolutional code can approach 60Mbit/s, the speed of four decoders working in parallel mode can reach 220Mbit/s. Finally, we test the performance of the (2,1, 7) convolutional code simply and analyse the test result.