The Research Of Thread Scheduling Technology In Dynamic SMT Architecture Base On EPIC

It is the development of parallelism extracting technology that leads the computing capability of microprocessor to be improved higher and higher. With the micro-architecture of superscalar and VILW becoming more and more full-blown, EPIC technology brings the development of ILP extracting to a higher circumstance. But not ILP extracting can satisfied the increasing requirement of computing capability, so, the new parallelism level, TLP (Thread Level Parallelism), is becoming the research hotspot in the computer research field. The DSMT architecture has more powerful ability to extracting parallelism with the method of hardware dynamic extracting and threads switching. EPIC expanding based on the DSMT architecture is a new meaning attempt.In this thesis, threads switching in the DSMT architecture based on EPIC technology are the major problem. The thread priority ordering, threads switching algorithms are proposed, including the designs of Preceded Multi-context Threads Buffer and Thread Switching Component. Among these, we modify the classical thread selection based on priority ordering and have the precise mechanism based on the switch event type to be added on, which improved the performance of thread selection. The Preceded Multi-context Threads Buffer has the virtue both of SMT and CMT, which can lodge 16 ready threads and make 4 of them activating. It can support the thread switching algorithm effectively. Also, the design of thread scheduling component and other parts are delivered in this paper.The algorithms and mechanism in this thesis improved the performance of classical SMT model, which can be proved with the result of simulation. The research of this paper benefits the future research work of SMT architecture based on EPIC.