Research And Implementation Techniques On Thread Scheduling Method And Its Testing Tools

With the development of multi-core technology, multi-chip multi-core architecture has gained more and more popularity on modern commercial middle or high-end servers. Multithread techniques based on software and hardware provides an effective mechanism for parallel computing, especially for transaction processing applications. With the increasing number of processor chips and cores, the new architecture brings about a new challenge on the design of the operating system scheduler and the optimization of the performance. The scalability and performance optimization of thread scheduling technology has become a research hotspot. The analysis and evaluation method on thread scheduling faces new requirements.In this paper, the principle of major schedulers and its key technology is analyzed firstly. The following is development trend of thread scheduling. At the same time, the approach to performance optimization of thread scheduling is summarized. Based on these discussions, the thread scheduling evaluation method is deeply discussed. Four performance evaluation aspects are presented. A detailed evaluation method is proposed according to each aspect. A three hierarchical testing model, at microstructure, modular construction and application program level is designed.A new test program called LTC aim to test the thread context switching cost is designed and implemented. In order to decrease additional overhead and to improve the accuracy and stability of the test result, LTC uses semaphore to realize the communication and the multithread synchronization. The context switch latency can be analyzed in varied situations by tuning the scheduling strategies, sharing models and workloads. Another analysis tools named BLT is implemented to evaluate the scalabilities of schedulers. Many workload and binding stratifies are also integrated into the BLT. The comparative result can be achieved by modifying the integrated strategies of BLT.Base on LTC, BLT, Sysbench and DBT2, a set of test programs simulating the thread competitive model is made up of to test scheduling performance. The theoretical performance analysis is further verified by the test result on O (1) and CFS scheduler. Some optimization design criteria on scheduling algorithm and strategy are put forward. For shechule algorithms, it is not only the cost of a single context switch, but also the application for transaction scheduling efficiency under heavy load should be considered. The scheduling optimization strategy among many cores is also of importance. The same application threads or very relevant threads run on the same core as far as possible.Tasks sharing no data or less data,should run on different cores. Under such distributing discipline, the miss rate of cache is reduced, the hardware resource utilization can be increased, and the overall system performance will be largely improved.The test method and tools provide a reference and an effective measure for scheduling technology research and analysis on multi-chip multi-core system. The research is supported by"Research on High-end Fault-Tolerant of Computer Architecture"project under National High Technology Research and Development Program (863 Program).