The Research And Implementation Of The Cache-Coherent Protocol Based On The OLSM Execution Model

The memory subsystem has been one of the main bottlenecks to improve the performance in modem microprocessor, both in superscalar processors with dynamic scheduling and in VLIW processors with static scheduling. The philosophy of the EPIC is to combine the advantages of superscalar with those of VLIW technologies. EPIC emphasizes static, explicit compiling by making full use of rich characteristics, such as concurrence dynamically, branch prediction and data speculation. Therefore, Memory Level Parallelism (MLP) becomes critical to resolving the performance bottleneck of the microprocessor.In the paper, an Optimized Lock Step execution Model(OLSM) was proposed from the point of view of hiddening memory latency and exploiting more MLP. Moreover, we designe and implement a Cache-coherent protocol based on the OLSM. The main work and originalities of this paper include the following four parts.Firstly, An Optimized Lock Step execution Model, OLSM, which can exploit more MLP, was proposed with research on the compiler latency semantics, and with thorough analysis of the basic EPIC Lock Step Execution Model and its deficiency.Secondly, according to the OLSM, a new kind of memory hierarchical structure that adapts to the EPIC architecture was constructed. Moreover, it was proved from theory and the actual SPEC2000 test that this new kind of structure can exploit a lot of memory resources and can develop more MLP, wherever in parallel programs/threads or in sequence ones.Thirdly, we thoroughly research on bus-based snooping mechanism and and the typical MESI protocol. And then we design and implement a Cache-coherent protocol which is high efficiency based on the particular memory hiberarchy of the OLSM.Last, we construct an automatic verification environment based on the multiprocessor system in order to fully verify the Cache-coherent protocol. Moreover, we do a logic synthesis about the main blocks which support the Cache-coherent protocol, and analyse the time delay. The result shows that the time delay meets system needs.The OLSM, the new kind of memory hierarchical structure based on the OLSM and the Cache-coherent protocol based on OLSM, which were proposed and implemented in the paper, were adopted in the design of the X microprocessor which was the first 64-bit high performance general microprocessor with EPIC philosophy in our country.