The Simulation And Implementation Of Cache Coherence In SCMP Based On Dual-ring Structure

Single Chip Multiprocessors (SCMP) system is one of the most important microprocessor architectures today. Cache coherence must be maintained in SCMP, as well as in conventional multi- processors system. There are two classic cache coherence protocols: snooping based, which will lead to long latency with the increasing of nodes and directory based, which will lead to more conflict in directory access. A new cache coherence protocol, "cache coherence based on dual-ring structure" is proposed to solve these problems effectively.This paper mainly focuses on the verification of the correctness and efficiency of this protocol. The cache with our dual-ring structure is divided into several modules at first. Then, key techniques in its design and implementation are discussed after analyzing the relations among these modules. And each module is described by Verilog-HDL. Finally, the cache with dual-ring structure is combined into our SCMP plat and several applications are selected to verify its correctness and to evaluate its performance.Simulation results show that this cache coherence protocol based on dual-ring structure can conquers the limitations in both snooping based protocols and directory based methods successfully. It can also improve the performance of the whole SCMP system.To estimate the hardware cost, this dual-ring structure is synthesized using FPGA Advantage for HDL Designer 5.4. Synthesis results indicate our cache coherence model satisfies the less design complexity and accessorial hardware cost requirement of on-chip systems..