Design Of An IP Core Compatible With Intel MCS-51 Series Microcomputer Based On EDA Technology

Since single-chip microcomputer (SCM) was invented, it has been applied widely in many fields because it is cabinet, flexible ,cheap and powerful. But with the coming of the communication age, the disadvantage of the traditional SCM was discovered because of its connatural structure defect. Its speed, scale and performance can't meet more and more requirements of the users. So the development and upgrade of SCM is faced with new challenges. After entering 1990s, the technology of the programmable logic integrated circuit entered developing period at full speed. The programmable unit of the device has counted and exceeded a million gates, SoPC (System on a Programable Chip) embedded with complicated function module has appeared. The complex programmable logic device breaks a new path for the reconstruction of SCM. Based on EDA technology and FPGA/CPLD (Field Programmable Gate Array/Complex Programmable Logic Devices), an IP Core Compatible with instructions of Intel MCS-51 Series Microcomputer was designed. This thesis mainly researches a method that uses EDA technology to design the IP core.This paper uses the top-down (Top-down) design method. According to the designing course, firstly, SCM was divided into different modules that the function was single. Secondly, every module was described with VHDL(Very High Speed Integrated Circuit hardware description language). Then all programs were synthesized and simulated with MAX+plus II. Finally, programs were downloaded to the FPGA/CPLD for the test carried on the hardware.The thesis used SE-5M EDA experiment system to carry on the test of the hardware grade. The programmable logic device in the experiment system is EPF10K10LC84-4 which belongs to FLEX 10K family (FPGA type) of Altera Company. Because the logic gate of EPF10K10LC84-4 device is limited, this thesis has been finished some of the modules'hardware grade test, such as ALU, Timer/Counter and SIU.Base on the result of our research, the method that uses EDA technology to design the structure of SCM is feasible. And FPGA/CPLD-based SCM accords with the development trend that the SCM should become faster, more efficient, miniature and integrated.