Research And Implementation Of RS Encoding And Decoding Algorithm

Error Correct Coding (ECC) and the Error-Control technology have played more and more important role in our life. ECC technology can improve the quality of communication by reducing the Bit Error Ratio (BER) in all kinds of digital communication systems and the recorder and operation systems in computers. The use of error-correction coding to eliminate the necessity of retransmission of the data is called Forward Error Correction (FEC). Reed-Solomon (RS) code is one of the most powerful and widely used coding schemes for FEC. Because the ability to correct both burst errors and random errors, especially the burst errors, RS code were widely used in the error-control schemes. In this thesis, on the basis of the encoding-decoding algorithms, their implementing paths and their relative technologies developed in these fields, we use the Decomposed Inversionless Berlekamp-Massey Algorithm to implement our design about the decoding of RS(204.188) code in xc2v1000 device of Xilinx VirtexII series. In this thesis, the parameter of RS code is (204,188) which can correct no more than 8 errors. Several aspects are included in the thesis:1. Analysis and compare with several general RS encode and decode algorithm.2. Several basis operations in GF including add, multiplication and inverse are discussed and then programming the operation in Matlab. A logic operation cell which can be implemented easily is used in our architecture by considering the time and area factor.3. The RS encoding algorithm is implemented by using the standard cell which is mentioned above.4. The architecture design of RS decoding algorithm is our emphasis. The algorithm includes several parts: Syndrome Calculator, Key Equation Solver, Chien Search and Error Value Evaluator. The design is implemented by using the Decomposed Inversionless Berlekamp-Massey Algorithm. This architecture achieves an optimization in the area-delay product.5. The Top-Down design methodology is used in our design and all modules are coding in Verilog-HDL. The design has been implementing in xc2v1000 device of Xilinx VirtexII series successfully. The maximal speed of the encode module can reach 162MHz in XST synthesis tool and the decode module's is 93MHz. The design can meet the requirement of high speed calculation.6. The design of the ASIC implementation about the algorithm is discussed simply. This will be our next step research.