Research And FPGA Implementation Of MELP Algorithm Parameter Codec Module

In the area of speech communications, low bit rate speech coding as one of speech coding methods has important significance in research, because it is low in bit rate and efficient in saving bandwidth. Among the existing low bit rate speech coding methods, mixed excitation linear prediction(MELP) is able to work in the bit rate of 2.4 kbps with relative good speech quality, so it has been widely used in secure and narrow band speech communication systems.When used in practical applications, a suitable hardware platform has a great impact on the applications of MELP algorithm. With the development of manufacturing technology, field programmable gate array(FPGA) creates new conditions for speech coding because of its characters in high integration, excellent sequence control and short development cycle.Thus, research of MELP algorithm implementation based on FPGA platforms has become a trend nowadays. Parameters encoding and decoding modules in MELP algorithm are the key parts, so the implementation of them based on FPGA has an important engineering significance.This thesis analyzes the quantification process of parameters in the encoding and decoding modules, discusses the design methods and key technologies used in FPGA platforms,implements and verifies the simulation of each module based on FPGA, and completes the performance analysis of each module. In details, Firstly, this thesis introduces the principle of MELP codec and classifies the parameters by the quantification methods they used and also discusses the extraction and quantification process of key parameters. Secondly, after the introduction to FPGA and development platform, the key technologies of FPGA design process including finite state machine(FSM), finite state machine and data path(FSMD),read only memory(ROM) and random access memory(RAM) are studied. Thirdly, after the analysis of fixed-point C language program, the bottom-up design procedure has been used during the design of each parameter codec module. All related modules, such as multidimensional left shift register module, pitch period quantification module, Fourier series quantification module, hamming error correction code module and data packing module, have been implemented by Verilog HDL in the Vivado design platform. In the process of FPGA implementation, the design of multidimensional left shift register reflects the bit process in FPGA. The pitch period and gain, which are in the scalar quantification module, totally embodies what FSMD does to data path and control path. The design of Hamming window and Fourier series that implemented by vector quantification protrudes RAM and ROM's ability to array problem. Finally, after the simulation, the output of each module has been verified.When evaluating the design performance, the LUTs and registers being used by each module has been analyzed, the results indicate that the modules designed in the thesis have a better performance both in the resource usage comparing the design results of the thesis to the results of Vivado HLS.