Font Size: a A A

Research And Design Of Bit Error Tester Based On Small RTOS51 And FPGA

Posted on:2006-06-08Degree:MasterType:Thesis
Country:ChinaCandidate:S Z QinFull Text:PDF
GTID:2168360152488768Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
Bit error tester is indispensable equipment during performance testing and malfunction diagnosis of communication system. With the enhancement of communication speed and more parameter needed to be tested, old bit error tester is not suitable for testing communication system because of its limits in digital processing and function extension. So we need to make a research on the kernel module of bit error tester and ameliorate it.In this paper, system requirement of Bit error tester is analyzed, and the system frame is worked out that is consisted of intelligent user interface sub-system and bit error test sub-system. In order to improve the system's integration and function expansion, bit error test sub-system is designed based on FPGA and application program of intelligent user interface sub-system is based on embedded operation system to achieve real time process.Old Bit Error Tester technique is studied。The principles of Pseudo-Random Binary Sequence, manual code, error bits insert and account of error bits are discussed; a synchronization adjudge module with synchronization protect is introduced. To send manual code and error bit test with high speed, multiplexer and demultiplexer are adopted. And the communication protocol is also worked out between sub-systems.According to the requirement of intelligent user interface sub-system, the hardware circuit is designed and all the function modules driver programs are introduced, including display module, real time module, data storage module, RS232 module and keyboard interface module.Some important characters of Small RTOS51 are studied including running condition, replantation measure. The reason of Small RTOS51 adopted is explained. According to the application software requirements, all the tasks are established based on Small RTOS51. And the attempter relation and flow chart of each task are recommended in detail.As this paper expressed, bit error rate tester design based on Small RTOS51 and FPGA realizes all modules required, shows a good performance of facility and stability. And the whole system has a good real-time attribute and expansibility because of using the embedded system.
Keywords/Search Tags:Small RTOS51, Bit Error Tester, driver program
PDF Full Text Request
Related items