Studies On Hierarchical Extraction Of 3-D VLSI Interconnect Parasitic Global Capacitance Matrix

With the feature size scaled down and work frequency increased, the parasitic parameters of interconnects have become dominant influencing the performance of VLSI circuits. For the timing verification with high precision, fast and accurate capacitance extraction of interconnects is required, especially in the current design of nano-scale integrated circuits with frequency above several GHz. This also improves the importance to extract the full coupling capacitance matrix of interconnects.In the recent years, some preliminary researches were carried out about the global computation based on the direct boundary element methods, such as the Macro-Model computation and zone partition method. Recently, our group proposed a new global method - Hierarchical Block Boundary Element Method (Hierarchical Block BEM) for 3-D interconnect capacitance extraction. This method is based on direct BEM and improves the computational efficiency greatly by transforming a large-scale problem into some small-scale problems and the reuse of computation.Based on the Hierarchical block BEM, this dissertation has made some improvement as following:A mixed partition strategy for 3-D BEM blocks is proposed. That makes the interfaces between blocks smaller. Therefore the efficiency of combination process is improved as a whole.An efficient nonuniform partition of boundary elements are proposed to adapt the character of interconnects in analog integrated circuit. That speeds up the computation of each leaf BEM block and combination of neighbor BEM blocks.A new reuse technology is proposed, which expand the reuse of BEM block computation into all of leaf BEM blocks, no mater how much and how complex the conductors in them are.The algorithm organization is improved. That reduces the space complexity to about 1/5 of before.All the above approaches have been implemented in the capacitance extraction program "HBBEM". The numerical results of several testing cases and real analog integrated circuit layout show that the improved HBBEM is about two times faster than the original HBBEM[2], with higher accuracy as well. Furthermore, more numerical results show that the adaptability and stability of HBBEM is improved much. Those make the improved HBBEM fit for the need of analog stimulation of real VSLI circuit.