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The Technique Study Of Ground Information Processing Of The High Speed And Big Volume Satellite Data Transmission System

Posted on:2003-02-17Degree:MasterType:Thesis
Country:ChinaCandidate:Y G YangFull Text:PDF
GTID:2168360092991941Subject:Control theory and control engineering
Abstract/Summary:PDF Full Text Request
The development of satellite and the rapid increase of communication capabilities demand data transmission system has the ability of high speed and efficient data processing and forward in addition the pole track sun synchronization weather satellite still require itself have the solid memory using to storage the big volume information, namely it provide the delay information storage -, process and forward function. Limited by the power and the bandwidth of satellite communication system . The characters of the channel of satellite communication determine that the technique if forward error correction can more efficiently provide better transmission bit rate and lower bit error rate. However the key of FEC technique is how to practically implement the error correction codec, which is also the most difficult to materially realize.However the actual development direction of space technique also is consistent with ground communication technique, namely it must based on a certain data communication protocol of the space . At present the standardization organize is NASA, ESA and the many country' s space bureau found the CCSDS(Consultative Committee for Space Data System), and recommend the CCSDS prepositional space navigation standard. The CCSDS standard protocol makes the data into high speed packet, multiplexing and the error correction codec; At the same time establish the virtual channel method , implement the multi-user share channel based on the TDM. On the other hand, the standard of data communication protocol of the space is not unalterable. As the communication, computer and the new technique of electronic design and manufacture using in the space field, those protocol also locate in ceaseless development. Often the design must rework because of the change of protocol, hence we must have the consideration for the thereafter system upgrade and change. The design of this paper follow such design thoughts, using the Reed_Solomon error correction codec is the recommendatory CCSDS RS[255 , 223]code, implement it via the high performance FPGA' s VHSIC Hardware Description Language, enhance the process speed, it can work at the speed of 93Mbps. Thus it transfer the ground information process system or some port to soft (the soft is the soft be in DSP> ASIC and FPGA). It makes the system base on the soft, it has the high flexibility and cost small.The function of the ground information process part of the data transmission system is the reverse process of information processing on the satellite, mainly fulfill the restore of information. The maths model of this system can be founded in the environment of MATLAB and simulate it in function.Reed-Solomon code (for short: RS code) is a kind of important cycle code, and is the best error correction codec of group code , it used widely in communication system and computer storage . Although RS codec has manypredominant performance, its decoding is comparative complexity. Whether using the hardware scheme or software, the RS codec also engross more resource correspondingly, thus searching a kind of economic and applied decode scheme is an important task in the field of the error correction codec. The RS hardware decode was implemented using the ASIC past, but the R&D' s cost is very high. But the development of PLD is fast at present, the performance is continually improved and the price is continually decline. The FPGA of Altrea' s APEX20KE series have the same performance as the SOPC, They are the first multi-core PLD based on the lookup table-> product-term and embedded storage block. I used a chip EP20K300E having the 300, 000 gate implemented the RS decode can correct 16 symbol error [255,223]. This paper in detail discussed the implement process of descrambling and RS decoding in the APEX20KE series FPGA.The design technique based on the PLD gradually becomes the mainstream in the digital signals processing design, using the programming hardware to implement some complicated arithmetic in the forward of data process. This can make the load comparativ...
Keywords/Search Tags:Satellite Information Process Technology, CCSDS, Synchronous, Scrambling and Descrambling, Reed_Solomn Encode and Decode
PDF Full Text Request
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