Improvement Design Of Central Processing Module On Digital ADCP

This project is a sub-part of the project,"A small multi-parameter marine environment detection buoy", in major project Marine Monitoring Technology under China national 863 programs. The task of the thesis is making the improvement design of central processing module.First, the function, history, theories foundation and central processing module at first system are introduced by this thesis. The first digital ADCP system has the advantage of cheap material, low consuming and multi-function. But the whole digital ADCP system, especial the central processing module cannot meet the future demand. In this thesis, the improvement design of central processing module and the debugging of improvement system are introduced detailedly. Finally, a new hardware design scheme of the central processing module is put forward. Meanwhile, I introduce the interface design between DSP (Digital Signal Processing) and exterior chips.This dissertation achieves the following points:1. In this thesis, I introduce a method to extend data space of DSP, that is the time-sharing multiplexing of two memories with the ingenious use of the probe in CPLD (Complex Programmable Logic Device).2. The various application of Verilog HDL and LPM(Library of Parameterized Modules)has improved the efficiency of the program design as well as the run rate of the system, when we use the logic design of the new CPLD chip.3. A new hardware design scheme of the central processing module is put forward.