Research And Implementation Of AIS Signal Receiving And Demodulation Algorithm

AIS is an automatic and continuous oversea broadcast system which is operated on VHF. It can be used to identify and communicate between ship and ship or between ship and shore unit. To enlarge the coverage of AIS, satellite-borne AIS (SAT-AIS) arises. It provides essential information for worldwide monitoring of any maritime mobile equipped with an AIS device. But SAT-AIS brings two problems:a large Doppler and signal collision. It means that SAT-AIS has become an essential component of worldwide maritime security. So the research on AIS signal demodulation has great theoretical and practical significance.In this thesis, a signal process system is developed for the actual demand, which is based on TI low power consumption and float-point processor TMS320C6748 and Xilinx Airtex7 series FPGA hardware platform. On this platform, implementation of signal’s demodulation and separation algorithm is carried out. Main research content of this paper includes:Research on AIS non-coherent signal demodulation algorithm is completed. Frame head detection, frequency offset estimation and symbol timing technology are introduced respectively in this paper. Comparisons of different methods about timing and frequency measurement are made. Meanwhile, Extensive research on the performance of signal demodulation affected by frequency offset and timing is carried out.Two or more signals from different ships can be received at the same time due to large coverage of satellites. When two signals have large difference in amptitude, the one with larger amptitude will be domodulated first. Then signal reconstruction is realized through sequence, signal’s amplitude, frequency and phase information. Separation is achieved finally.Based on Artix-7 platform, frame head detection module is accomplished in this paper. In the same way, based on TMS320C6748, the AIS baseband signal demodulation module is accomplished. In addition, detailed solutions and analysis are given out about the problems encountered in process. Implementation of each module is demonstrated. Interconnection communication between DSP and FPGA is realized through EMIF. Communication between DSP and PC is realized through UART. Finally, the function and performance of the whole system are tested.