Research On Related Techniques For Low-Power FPGA Design

Abstract:Field programmable gate array (FPGA),as a programmable logic device,has gradually evolved over the last twenty years from a peripheral component of an electronic design to a core processing element of digital systems,which is widely used in various field of prototype,computer hardware,industrial controlling,communications, automotive electronics,aerospace,etc.With the constant improvement of the integrated circuit manufacturing technology and the growing increase of the speed,scale and complexity of FPGA device,the FPGA design is facing a series of new problems,one of which lies in the problem of power consumption.This dissertation carries out a research into the design of FPGA power consumption and then puts forward many practical and effective technologies and methods for low power consumption. The main research work and innovative achievements are listed as follows:(1)On the basis of deeply analyzing the source of static random access memory(SRAM) leakage current, a new design method of low power SRAM suitable for PFGA the paper is proposed. According to the characteristic that most SRAM cells is storing "0" when FPGA is configured,the proposed method reduces the leakage power dissipation of SRAM when the SRAM cell stores "0" by using dual threshold voltage technique and dual oxide thickness technique. The method has the advantages of improving the static noise margin of SRAM,together with reducing leakage power dissipation without increasing the circuit delay and area.(2)Aiming at the phenomenon of the used multiplexers in FPGA containing many idle transistors,a new design method of multiplexers suitable for FPGA low power the paper is proposed. The proposed method optimizes the leakage power dissipation of idle transistors in multiplexer by using reverse body bias technique and reduces the total leakage power dissipation while maintaining performance.(3)Based on the source analysis of FPGA power consumption in different states and combined with advantages of dual-Vdd and power gating technologies to reduce the power consumption of FPGA in different states, a new design method of FPGA lower-power architecture is proposed. The FPGA device designed with this architecture has the advantages of reducing the dynamic power consumption and static power consumption,which is especially suitable for application in mobile and handheld devices.(4) In the aspect of FPGA application design,against the shortcomings of occupying more routing resource and high power in traditional register files implement method,a new design method of lower power register files based on block RAM in FPGA is proposed. The simulation results show that compared with the traditional ways the new method has the advantages of reducing power consumption,saving routing resource and being easy to implement.(5)Considering the reliability and power consumption problems of FPGA in aviation and spaceflight application field,a new design method of low power and fault-tolerance finite state machine suitable for FPGA is proposed. The method is realized by mapping finite-state machines (FSM) into embedded blocks RAM of FPGA and employing two RAM blocks to compose the duple-redundancy structure to confirm data errors in RAM through comparing consistency of two blocks RAM output data and combining with parity check for error detection and correction. Compared with the traditional triple-redundancy method, the FSM designed with this method has the advantages of lower power,higher reliability,and achieving an error on-line error correction.