Self-aligned insulated gate FET technology for indium phosphide: An interfaceengineering approach

In this study, we present a new approach by combining a novel indirect plasma deposition technique with sulfur (S) surface passivation to engineer a low trap interface that shows good high temperature stability and a highly reproducible SAGFET technology has been developed that shows promise. The first phase of this study concentrates on the nature of S passivation of InP by PL and XPS measurements. The results clearly show thermal S passivation leads to the formation of a 30A In;S passivated Metal/silicon nitride/InP (MIS) capacitors with near ideal C-V characteristics, negligible hysteresis and midgap interface state density in the low ;The study clearly reveals the advantages of using interface engineering techniques for next generation insulated gate high speed devices for InP and is expected to inspire the development of a mature interface engineering technology for III-V semiconductors. (Abstract shortened by UMI.)...