| Fault tolerance in computer systems is important for insuring correct operation for such applications as satellites, airplanes, and banking. Fault tolerance techniques can be applied in many ways to computer systems, from high level software to basic hardware structures. A particular research focus is digital arithmetic units, where various forms of redundancy allow for concurrent error detection or correction. Basic approaches are hardware redundancy, information redundancy, and time redundancy. Application of time redundancy to more complex arithmetic structures, such as fast multipliers and dividers, has not been examined thoroughly.;The purpose of this research is to study the application of Time Shared Multiple Modular Redundancy (TSTMR), also known as REcomputing with Triplication With Voting ( RETWV), to fast multiplication and division. Multipliers based on the Reduced Area approach and dividers based on either the Newton-Raphson algorithm or Goldschmidt's algorithm are designed and evaluated at the logical gate level. Various properties of nominal, TMR, and TSTMR designs are compared. These properties include area, cycle time, latency, fault coverage, and power consumption. |
