| This dissertation is a study of the current leakage mechanisms and hot carrier reliability of Silicon-on-Insulator (SOI) p-channel MOSFET's. The results of this work are very timely, as they coincide with the adoption of SOI CMOS technology by the semiconductor industry as a mainstream technology for advanced low-power/low-voltage applications.; As the channel length continues to shrink towards and beyond 0.1 microns and the gate oxide down to 50 Angstroms or less, the control of two very important leakage mechanisms becomes crucial to SOI CMOS technologies, namely: Drain Induced Burrier Lowering (DIBL) and Gate Induced Drain Leakage (GIDL). Both these mechanisms are far more important in p-channel devices compared to n-channel. DIBL is strongly enhanced by hot carrier injection, and the worst-case degradation conditions are established. Both DIBL and GIDL depend on drain structure design. It was further found that DIBL and GIDL are strongly interdependent, and our results point to design trade-offs for obtaining optimal device structures with low leakage and high reliability.; Leakage and reliability also depends on channel width. It was found in this dissertation that both DIBL and GIDL decrease with channel width, the single transistor latch-up improves, and the hot carrier reliability worsens. These experimental observations are all explained by the concept of pseudo-body ties, introduced for the first time in this dissertation. According to this idea, Boron out-diffuses at the source- and drain-edges, resulting in relatively low-doped, narrow strips of silicon along the channel edges, resembling body-ties, with their well known consequences. This new concept, together with the consideration that in p-channel SOI MOSFET's impact ionization and hence floating body effects are not as important, are able to explain the observed device behavior with channel length, as well as the differences between n-channel and p-channel transistors.; Finally, this dissertation develops a sensitive tool for the evaluation of the quality and reliability of the buried Si/SiO2 interface of SOI structures, which is based on a variation of the gated-Diode technique. This was applied both to study as-grown interfaces as well as hot carrier degradation. |
