The design, fabrication and characterization of non-elevated and elevated source/drain p-channel MOSFETs for deep submicron technologie

The integration of P-channel MOSFET devices for deep-submicron technology generations was examined in this work. MOSFET gates, dielectrics and junctions were studied with the objective of evaluating specific alternative materials and structures that address scaling requirements. Several grown and deposited oxide, oxynitride and stacked gate dielectrics were evaluated as potential replacements for furnace oxides to address the projected failure of pure thermal oxides in restricting boron penetration and tunneling gate leakage below 2.0 nm. An alternate device structure, the Elevated Source/Drain (ESD) MOSFET was examined to alleviate scaling bottlenecks in silicided junction formation.;Evaluations were conducted separately for channel and junction parameters in the context of a 0.1 mum PMOS technology. Device designs were optimized using statistical Design of Experimentation (DOE) and Response Surface Analysis (RSA). Channel optimization was performed for both implanted and uniformly doped channels, and individually for four gate dielectric formation techniques: Furnace oxides, Rapid Thermal Oxides (RTO), Rapid Thermal CVD (RTCVD) oxides and Remote Plasma Enhanced CVD (RPECVD) Oxides. Optimized devices having implanted channels showed a 9.4% improvement in saturation drive current over uniform channel devices.;Dielectric performance was evaluated with respect to interface state densities, gate leakage and boron penetration. Excellent resistance to boron diffusion was obtained with RPE oxide/nitride stacks. Limited resistance to penetration was also observed for RTCVD oxides. RTO oxides showed the lowest leakage, although broadly acceptable leakage characteristics were seen for all dielectrics. The oxide/nitride stack dielectrics were found to best meet gate insulator requirements for sub-2.0 nm thicknesses.;Junction structures with an elevated source/drain scheme were-specifically considered for their potential to provide low-resistivity, thick-silicided, shallow junction configurations. Several process integration issues associated with elevated junction formation by Selective Epitaxial Growth (SEG) in an ESD technology were studied. The impact of epi selectivity and overgrowth on process integration issues was studied. A high epi selectivity allows the polysilicon capping layer to be eliminated, resulting in process simplification, while moderate epi selectivity is found to be more conducive to borderless contacting.;Facet evolution during SEG and Epitaxial Lateral Overgrowth (ELO) was characterized to understand the impact of scaling on facet morphology. Facet development as a function of epi thickness was investigated for selective epitaxial growth bounded by vertical, horizontal and tapered dielectric surfaces. Based on a two stage growth process, growth rates were determined for the different facet planes during lateral overgrowth.;The impact of faceting on silicidation induced junction leakage in fabricated ESD PMOSFETs was investigated to characterize the risk of junction penetration at silicided facet edges. The leakage in ESD junctions was found to be higher at isolation boundaries than at gate boundaries, and lower when the substrate junction was deeper, indicating that silicide penetration into the substrate occurred at the facet edges. Epi processes, with moderate rather than high selectivities, are recommended to reduce the extent of silicide penetration by increasing lateral overgrowth at the isolation edge. (Abstract shortened by UMI.).