Four Terminal Gallium Nitride MOSFETs

All reported gallium nitride (GaN) transistors to date have been three-terminal devices with source, drain, and gate electrodes. In the case of GaN MOSFETs, this leaves the bulk of the device at a floating potential which can impact device threshold voltage. In more traditional silicon-based MOSFET fabrication a bulk contact can be made on the back side of the silicon wafer. For GaN grown on sapphire substrates, however, this is not possible and an alternate, front-side bulk contact must be investigated.;GaN is a III-V, wide band gap semiconductor that as promising material parameters for use in high frequency and high power applications. Possible applications are in the 1 to 10 GHz frequency band and power inverters for next generation grid solid state transformers and inverters. GaN has seen significant academic and commercial research for use in Heterojunction Field Effect Transistors (HFETs). These devices however are depletion-mode, meaning the device is considered "on" at zero gate bias. A MOSFET structure allows for enhancement mode operation, which is normally off. This mode is preferrable in high power applications as the device has lower off-state power consumption and is easier to implement in circuits.;Proper surface passivation of seminconductor surface interface states is an important processing step for any device. Preliminary research on surface treatments using GaN wet etches and depletion-mode GaN devices utilizing this process are discussed. Devices pretreated with potassium pursulfate prior to gate dielectric deposition show significant device improvements. This process can be applied to any current GaN FET.;Enhancement-mode GaN MOSFETs were fabricated on magnesium doped p-type Wurtzite gallium nitride grown by Metal Organic Chemical Vapor Deposition (MOCVD) on c-plane sapphire substrates. Devices utilized ion implant source and drain which was activated under NH3 overpressure in MOCVD. Also, devices were fabricated with a SiO2 gate dielectric and metal gate. Preliminary devices exhibited high GaN-oxide interface state density, Dit , on the order of 1013 cm-2· eV-1.;Additional experiments and device fabrication was focused on improving device performance through optimization of the ion implantation activation anneal as well as incorporation of a bulk p-type ohmic contact and migration to a thicker, lower defect density, HVPE-grown template substrate. The first reported MOSFET on HVPE grown GaN substrates (templates) is reported with peak measured drain current of 1.05 mA/mm and a normalized transconductance of 57 muS/mm. Fabricated devices exhibited large (greater than 1 muA) source-to-drain junction leakage which is attributed to low activated doping density in the MOCVD-grown p-type bulk.;MOSFETs fabricated on template substrates show more than twice the measured drain current as similar devices fabricated on traditional MOCVD GaN on sapphire substrates for the same bias conditions. Also, template MOSFETs have decreased gate leakage which allowed for a much greater range of operation. This performance increase is attributed to a more than doubled effective channel mobility on template GaN MOSFETs due to decreased crystal defect scattering when compared to a MOCVD-grown GaN-on-sapphire MOSFET. Fabricated MOSFETs also exhibit decreased interface state density with lower bound of 2.2x1011 cm-2·eV-1 when compared to prelimary MOSFETs. This decrease is associated with the use of a sacrificial oxide cap during source/drain activation. Suggested work for continued research is also presented which includes experiments to improve source/drain ion implantation profile, utilization of selective area growth for the active area, improved n- and p-type ohmic contact resistance and investigation of alternate oxides.