Device modeling, analysis and fabrication of Indium0.53Gallium0.47Arsenic field-effect transistors

Since the invention of silicon CMOS (Complementary Metal Oxide Semiconductor) transistors, the great scalability of silicon technology has led the entire semiconductor industry. Following Moore’s law, the number of transistors is approximately one billion in a chip at the 22 nm technology node. However, the power consumption, which is the sum of dynamic and static power dissipation, becomes a critical issue to the further advance of silicon transistors for the high-speed, low-power logic applications. While maintaining the device performance at ON and OFF state, the novel device design and materials are inevitably required, facilitating the supply voltage scaling. In this regard, III-V semiconductors such as InAs, InSb and InxGa 1-xAs (x≥0.53) with superior channel transport have attracted a great interest.;Recently, planar and non-planar FETs (Field Effect Transistors) with III-V compound semiconductors are under intense research and they have exhibited comparable device performance to silicon technology with lower supply voltage. The expected enhancement in device performance is originated from the excellent electron transport property at both low and high electric fields arising from low Γ-valley electron mass. On the other hand, the several challenges facing the III-V compound semiconductor community are (1) the scalability of III-V FETs in terms of gate-length and gate-pitch, (2) the improvement of the interface between high-k dielectric and III-V compound semiconductors, (3) the integration of III-V materials on silicon and (4) the development of suitable p-type MOSFET for the CMOS configuration.;This dissertation presents first the understating of the carrier transport in III-V FETs. Based on this, we investigate the scalability of III-V FETs in terms of gate-length and gate-pitch by 2-dimensional drift-diffusion simulation. Furthermore, since the announcement of non-planar, tri-gate silicon transistors at the 22 nm technology node, the scalability of gate-pitch in non-planar III-V transistors with suitable contact architecture is also of great importance and is investigated by 3-dimensional drift-diffusion simulation. Experimentally, the interface quality at high-k dielectric/III-V material with different surface treatment is demonstrated. Furthermore, the introduction of solid phase regrowth (SPR) process on heavily-doped and lightly-doped In0.53Ga 0.47As samples is explained in order to achieve the low contact resistance. This is followed by the experimental demonstration of non-planar, tri-gate In0.53Ga0.47As transistors with two different contact architectures; planar contact scheme and non-planar (surrounding) contact scheme. In order to boost ON-current at extremely scaled gate-pitch for future technology node, the importance of contact strategy is highlighted and the further possible improvement is discussed.