| The dominant device used in modern VLSI circuits is the MOS transistor. As technology has advanced, several limitations of MOSFETs have become apparent: hot electron effects, short channel effects, and also the practical technological problems of shrinking junctions and growing high integrity, low defect, thin gate oxides. MESFETs do not require thin gate oxides and hence are not susceptible to the problems of either obtaining reliable thin gate oxides or to many of the problems of hot carriers. In addition, MESFETs are naturally radiation resistant and, for scaled devices, have superior carrier mobility over surface conduction devices. N channel silicon MESFETs have shown competitive speed-power performance compared to MOSFETs, but the limited variety of circuit configurations has greatly limited their use. By developing a complementary MESFET process, greater speed can be achieved with lower power dissipation, while simultaneously improving circuit flexibility, thus improving their viability for VLSI applications.; We present the development of a complete complementary MESFET technology. The state-of-the-art, fully implanted, CMOS-like process uses Shannon implants together with a refractory silicide Schottky gate material to combine high gate barrier heights with ease of fabrication. To minimize parasitic resistances, a unique gate structure and sidewall spacers are utilized to allow for self-aligned implantation of the source/drain regions. A self-aligned titanium silicidation technique is employed to minimize sheet and contact resistance of the source/drain regions. The SUPREM process simulator was employed extensively and is compared with physical and electrical measurements (e.g., spreading resistance and sheet resistance measurements). High drive complementary silicon MESFETs were successfully fabricated using the technology outlined above. The performance and modeling of device parameters (e.g., threshold voltage, transconductance, short channel effects, and transient measurements) and circuit parameters (e.g., standby current, noise margin, and speed) is accomplished through analytic formulations, the PISCES two-dimensional device simulator and the SPICE circuit simulator. In addition, data on the low temperature operation and the radiation hardness of the devices is presented. |
