Modeling Layout Dependent Stress Effects for CMOS

Process induced mechanical stress has enabled continued CMOS scaling since the 90nm node to improve carrier transport and maintain high drive current. This stress depends strongly on the layout shape as well as the surroundings of each transistor in a circuit. The resulting stress variation changes the individual transistor performance and circuit delay which lead to yield loss. Therefore, analytical stress models are needed to relate these stress dependent variations to critical layout parameters for design optimization.;This dissertation presents the development of accurate, non-process specific analytical stress models which are capable of analyzing systematic layout induced mechanical stress variations. The process and layout dependence of all relevant process induced intentional and unintentional stress sources has been incorporated into our analytical models. Intentional stress sources are embedded lattice mismatch stressors (LMS) and contact etch-stop liners (CESL), whereas unintentional ones are shallow trench isolation (STI) and through silicon via (TSV) stress.;Analytical models are calibrated and verified against silicon ring oscillator frequency data. The models exhibit a very good fit to the silicon data and resulting root mean square error (RMSE) between silicon and model results is less than 0.8%.;The created analytical models can be employed by circuit and layout designers to quickly optimize their layout and reduce stress dependent performance degradations without using technology computer aided (TCAD) design tools which are very slow and impractical to be used in circuit design environment.