Novel techniques to increase capture range of clock and data recovery circuit

The Hogge-type linear full-rate CDR is widely used in the receiver of broadband communication systems, because of its good steady-state jitter performance. One of the biggest challenges in the design of a linear CDR is its inherent limited capture range. This dissertation investigates how the strobe point shift and the monotonic range reduction can lead to reduction of the capture range. To simplify the nonlinear and complicated pull-in process, the output current of the phase detector is approximated by a piecewise-linear function. The simulation results verify the accuracy of the model calculation. The analysis shows that reducing the gain of the PD, the loop filter and the VCO will all degrade the capture range in the presence of a non-zero strobe point, and gives more insight into the trade-offs in the performance parameters of a CDR, such as the jitter transfer bandwidth, jitter peaking, and capture range. Though the presence of a non-zero strobe point is the key issue for a linear CDR with respect to the reduction of the capture range and the jitter tolerance, the analysis in this dissertation shows that the "single-sided" capture range enhancement can be used as a frequency detector if the polarity of the strobe point is selected correctly. Based on this concept, a novel 8.2 - 10.3 Gb/s referenceless CDR architecture fabricated in a 0.18-microm BiCMOS process is presented. The most important feature of this architecture is that the linear phase detector detects the frequency difference in the frequency acquisition mode so that a dedicated frequency detector is not needed, which reduces the power dissipation considerably. The measurement results show that the capture range of the proposed CDR is from 8.2 Gbps to 10.3 Gbps with moderate power consumption (174 mW at 1.8 V power supply voltage). To further improve the performance of the jitter tolerance, a phase adjustment mode is included. The measurement results show that the jitter tolerance is 0.58 UI, and the rms random jitter is only 0.336 ps at the 10.3 Gbps input bit rate.