Design of high-speed optical interconnect transceivers

The increase in computing power enabled by CMOS scaling has created increased demand for chip-to-chip I/O bandwidth. Unfortunately, inter-chip electrical channel bandwidth has not scaled similarly to on-chip performance, causing current high-speed I/O link designs to be channel limited and require sophisticated equalization circuitry which increases power consumption. Interconnect architectures which employ optical channels have negligible frequency dependent loss and provide a potential path to increased I/O bandwidth without excessive circuit complexity or power consumption.; This dissertation focuses on a dense low-power CMOS optical link architecture which employs novel optical transmitter and receiver circuits and leverages an electrical link technique of time-division multiplexing in order to achieve high-speed operation. Transmitter designs are demonstrated for the two primary high-density optical sources, vertical-cavity surface-emitting lasers (VCSEL) and multiple-quantum-well modulators (MQWM). The implemented VCSEL driver employs simple transmitter equalization techniques in order to extend the effective device bandwidth for a given reliability level. For the MQWM devices, a pulsed-cascode driver supplies an output voltage swing of twice the nominal CMOS power supply without overstressing thin oxide core devices. A low-voltage integrating and doublesampling optical receiver provides adequate sensitivity in a power-efficient manner by avoiding linear high-gain elements. In order to address this receiver's inability to handle uncoded data, a swing control filter which actively clamps the input signal within the receiver input range is investigated.; Transmitter clock generation uses an adaptive bandwidth phase-locked loop (PLL) for a wide frequency range, while receiver timing recovery is implemented with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption. High-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers applied independently on a per-phase basis.; Implemented in a standard 1V 90nm CMOS process, the transceiver operates at data rates between 5 to 16Gb/s. At 16Gb/s, the measure power consumption is 129mW for the VCSEL-based link and projected at 103mW for the modulator-based link, with both links occupying an area close to 0.1 mm2.