Adaptive power control for WCDMA RF power amplifiers with antenna mismatch

This dissertation proposes an alternative power management architecture for WCDMA (wideband code division multiple access) transmitters to further improve the system efficiency by combining an adaptive RFPA (radio frequency power amplifier) power supply with an adaptive tuner between the RFPA and the antenna. A power management controller detects antenna mismatch and controls a tunable matching network and the adaptive power supply in a closed-loop manner. With real-time detection of the antenna mismatch condition, the controller adjusts the matching network to match the RFPA to O 50 impedance, which reduces power reflection from the antenna and eliminates the need for the lossy isolator. It is shown that a significant improvement in efficiency is possible with a combination of adaptive RFPA supply and impedance tuning for the transmitter having an antenna mismatch. Also, a 2 dB improvement in maximum output power is obtained.;A non-inverting buck-boost power converter is used to realize the adaptive RFPA supply. The issues of limit cycling in a standard analog controlled non-inverting buck-boost converter during buck/boost mode transition are investigated. The investigation is validated experimentally and the results are predicted using theoretical analysis. Furthermore, a Sigma-Delta modulated digitally controlled non-inverting buck-boost DC-DC power converter is proposed to solve the limit cycling problem identified in the analog controller. This controller enables a smooth buck/boost mode transition without limit cycling. Furthermore, a 2-mode PID (proportional-integral-derivative) compensator is presented which improves closed-loop dynamic performance compared to a conventional, single mode PID. Results on smooth transition and transient performance of the power converter are experimentally verified.;Finally, an IC (integrated circuit) implementation of a digitally controlled non-inverting buck-boost power converter is reported. The IC includes the Sigma-Delta modulated digital controller, on-chip power stage and a low power second-order Sigma-Delta ADC (analog to digital converter) in a 0.5 mum CMOS (complimentary metal oxide semiconductor) technology. The total quiescent power consumption of this IC is 700 muA. The design methodology and the effects of combining the Sigma-Delta DPWM (digital pulse width modulator) with the Sigma-Delta ADC for output voltage regulation are reported. This non-inverting buck-boost IC is a complete implementation of a low-power digitally controlled power converter with wide input output voltage conversion range.