Design Of Digitally Controlled Oscillator (DCO) For GSM Transceiver

This work shows the design of a digitally controlled oscillator (DCO) for quad-band GSM transceiver in 90 nm CMOS process. Each chapter covers modeling and analysis of both conventional phase locked loop (PLL), oscillator and all digital phase locked loop (ADPLL) and DCO. Detailed modeling, design analysis and optimization methods for design specification are performed.The main contribution of this work is the proposing of a novel way to improve the frequency resolution of DCO. This structure passes the physical limitation of process decreasing the difference of capacitor so that the frequency resolution and oscillator phase noise have been enhanced.The characters and principle of DCO are described at first. Then the proposed novel series switched varactor model is analyzed. The fine tuning capacitor bank in DCO is then implemented using this varactor to achieve better frequency resolution. A DCO in 90 nm CMOS process using this new structure achieves a frequency resolution of 1.6 kHz without dithering and a phase noise of -152 dBc/Hz at 20MHz offset when oscillating at 3.1 GHz. The total power consumption is 8.16 mW.This work demonstrates this frequency resolution enhanced DCO is capable for the application in ADPLL for quad-band GSM transceiver.