The Study On The Model And Structure Of Novel Tunnel Field Effect Transistors

As the feature size of the metal-oxide-semiconductor field effect transistors(MOSFETs)is scaled down to the nanoscale,almost to its physical limitation,the increased cost,degraded stability and the increased power dissipation induced by further scaling have already become to be the main obstacle for the further development of the integrated circuits(ICs).Compared with the conventional MOSFETs,tunneling field effect transistors(TFETs)based on the quantum tunneling mechanism can break the Boltzmann limitation in the thermodynamic transport and therefor the subthreshold swing(SS)at room temperature can be lower than the MOSFET limitation of about 60 mV/dec,which is helpful to further reduce the supply voltage and suppress the leakage current.Thus,the power dissipation in a circuit can be also decreased.At present,the TFET with corresponding circuits draws intensive attention in the microelectronics and is regarded as the most promising candidate of the MOSFET to promote the further development of the high-performance and low-dissipation ICs in the Post-Moore era.Although a lot of research has been carried out for TFETs,there are still several problems.(1)There is no reported TFET that can simultaneously achieve both high on-state current and low sub-threshold swing.(2)There is no analytical model that can accurately simulate the terminal current and capacitance of TFETs.(3)There is no one reported model for the transient current and high frequency capacitances of TFETs,which definitely limits the application prospects of the TFET devices and circuits.(4)The current cannot be regulated by the channel length like that of MOSFETs.This is difficult to meet the flexible requirements of different driving capacities in practical circuit design.In addition,for the vertical structures used in compound devices,there are still some problems,such as the incompatibility of process flow with traditional CMOS process and the difficulty of achieving higher performance of heterogeneous integration and TFET-CMOS hybrid circuit design.In this dissertation,the main problems of TFET research are studied.The innovation and the achievement in our work are as shown below.(1)Analytical models for the drain current(IV)and the terminal capacitances(CV) considering the source depletion width and channel mobile charges.Compared with other models,the model developed in this dissertation takes the influence of both the mobile carriers and the source depletion width into account.It can predict the output performance and the terminal capacitances with promoted accuracy owing to the more comprehensive physical effects.In addition,without involving any iterative process,the model is totally analytical and can be more compatible with the widely used SPICE simulations.Finally,it can be also used for the novel hetero-gate-dielectric(HGD)structures which can improve the Miller capacitance significantly in a TFET.Compared with the numerical modeling and table look-up method,this model is in low hardware-requirement and more efficient,which indicates that it would be helpful for the TFET-based circuit,especially large scale circuit simulations.(2)Relaxation time approximation based models for the transient current and high frequency capacitancesBased on the proposed potential and electrical models,the relaxation time approximation(RTA)is adopted to develop the transient model of the channel charges and then the model of the transient gate current and the high frequency capacitance are also established.Good agreement between the model results and the numerical simulations is obtained.In addition,a method for the extraction of the relaxation time from the measured or simulated data is exhibited.The influence of the device structure such as the oxide dielectric,channel length and the channel thickness on device performance can be well described by our model.This is the first model for the transient and high-frequency performance of TFETs.With the capability of extending the frequency band of TFET-based circuit simulations,it is helpful for the high-frequency applications of TFETs.(3)A novel planar device structure compatible with the traditional fabricationA novel planar device structure for TFETs is proposed.Taking the InAs/Si heterojunction as an example,the basic working principle,non-ideal effects and the device parameters are studied in detail.The following three points should be noted for the proposed planar structure.First,it allows for TFETs based on the heterojunction with compound material compared with other planar devices and therefore is promising for improved on-state current owing to the reduced tunneling barrier width.At the same time,it is compatible with the conventional CMOS fabrication,which is of significance for cost saving and the TFET-MOSFET hybrid design.Secondly,the proposed structure shows good material universality and is suitable for many kinds of material systems,such as InAs/Si,Ge/Si and GaSb/InAs.Furthermore,it can be used for both the nTFET and pTFET,which is extremely significant for the complementary TFET circuits design.The third is that the gate is placed to be parallel to the tunneling junction in the new structure,which increases the effective tunneling area and thus leads to improved tunneling current.Moreover,different from that in the conventional device the tunneling current cannot be adjusted by the device geometry,the drain tunneling current in the new device can be modulated by the effective tunneling length linearly.This allows that circuit designers have more choice about the current magnitude and increases the design flexibility.In conclusion,analytical drain current and terminal capacitance models are developed,based on which the transient gate current and the high-frequency capacitance models are also proposed by the aid of the RTA method.The proposed models are totally analytical and can be easily applied to the widely used SPICE simulations and would be helpful for the TFET-based circuits.In addition,the new planar device structure provides new way for research and more promising development prospects,and exhibits profound guiding significance for further investigations on device mechanism and performance improvement of TFETs.