High-level Power/Energy Estimation And Optimization For Real-time Wireless Communication System Early-stage Design

From code division multiple access(CDMA)technology used in 3G to MIMO-OFDM and carrier aggregation(CA)technologies in 4G,data rates have considerably increased,and will be further increased up to 10 Gb/s or more by the upcoming 5G technology.The rapid evolution of commercial wireless communications technology has dramatically changed the way human interact and significantly altered people's lifestyles.However,this is also accompanied by an increasing share of global greenhouse emissions and energy consumption.Green communication technologies currently receive a lot of attention,which aim to drastically improve energy efficiency of wireless networks without degradation of user QoS/QoE.Consequently,based on digital signal processing techniques and embedded system design methodologies,this thesis investigates the power/energy modeling of base stations and low-power design methodologies for base station system early-stage design.The goal of the thesis is to provide power/energy metrics and analysis tools for 5G system early-stage design,e.g.,assessment/comparison of candidate system designs,exploration of energy-efficient transmission strategies and system configurations.The main novelties and contributions are:1.Multilevel power and energy modeling of real-time digital signal processing subsystem in base station is proposed.Firstly,based on the LTE physical layer standard,the design process of the embedded real-time digital signal processing system is investigated in order to identify the influence of wireless communication standard specification,algorithm complexity,hardware architectures of algorithms,hardware platform types(e.g.,DSP/FPGA/ASIC)and low-level basic components(e.g.,adder/multiplier)on the system power/energy consumption.Then,a multilevel and cross-platform power/energy model is built based on algorithm sets,microarchitecture sets and basic components(or standard cell library)sets.Such multilevel model can reflect the corresponding relationship between the configuration at system-level and low-level hardware utilization,which is benefit to make sure the system power/energy corner and explore the energy-efficient configurations in early design stages.2.A two-step power/energy estimation method based on multilevel power/energy model is proposed for real-time digital signal processing system power/energy estimation in early design stages.On the one hand,relative power/energy estimation method is presented in order to compare the candidate system designs in early design stages.All of the basic components used in candidate designs need to be collected and make a definition about power consumption.Relative power then is estimated by using the proposed multilevel power/energy model and the defined components power.Although there exists the estimation error between the relative power/energy estimation and actual power consumption of candidate designs,such error has no impact on the comparison results.On the other hand,additional absolute power/energy estimation method is proposed to help digital system designers to make power or energy budget in early design stages.Because of the high estimation precision required for power/energy budget,several functional modules of target system(but not whole design)are needed to be selected and measured the power/energy consumption at register transfer level or below.By using the calibrated power/energy of selected modules and the result of relative power/energy estimation method,i.e.,the power/energy proportional distribution of all functional modules in specified design,absolute power/energy of whole design is estimated.In this thesis,such two-step power/energy estimation method has been applied to an LTE eNB power and energy estimation,and the comparison result shows that it is near accurate.3.A(multilevel power/energy)model-based optimization method is proposed for early-stage task scheduling(time allocation)and low-power design of MPSoC-based hard real-time digital system.In terms of hard real-time embedded system with complex functionality,a series of task usually has to be done under specified timing constraints(QoS requirement).Consequently,in early design stages,it is necessary to determine the deadline for each real-time task executed by the target system in order to design hardware architecture of system.Hence,specified hardware architecture of each task or whole system can keep target system away from the time violation.Under specified timing constraints of the whole system,there are various ways for time allocation of each task.It is a NP-hard problem.In this thesis,a optimization method based on the multilevel power/energy model is proposed to solve this problem.Meanwhile,this optimization method also can be applied to low-power design of MPSoC-based hard real-time system.Especially,in early design stages,this method can help system designers to make right decision on the maximum parallelism of the hardware architecture for each real-time task under the minimum power consumption.4.Generic power models of analog subsystems in base station,i.e.,radio frequency(RF),power amplifier(PA)and analog-to-digital/digital-to-analog converter(ADC/DAC),are proposed.Firstly,the circuit structures and power consumption factors of the RF,PA and ADC/DAC are investigated.Then,in terms of RF and ADC/DAC,the generic statistical power models are built according to existing RF and ADC/DAC design cases.Such statistical power models can provide a clear picture of current situation and future trend of RF and ADC/DAC power consumption for designers.Furthermore,such statistical power models can help analog system designers to estimate power dissipation,select suitable components and to identify low-power design entry points in early design stages.On the other hand,a PA power model is also proposed by analyzing its principle,circuit structure,silicon technology and so forth,which provides more configurable parameters for designers to estimate power consumption of candidate PA designs.The comparison result shows that maximum power estimation error of the proposed power amplifier power model is 31.8%.5.A software platform based on the proposed models and optimization methods has been developed.This platform will be further improve the estimation speed and utilization of estimation models.