Research On Architectural Level Power-Gating Optimization For Network-on-Chip

In recent years,Network-on-Chip(NoC)has been proposed as the mainstream architecture to connect various on-chip IP cores in many-core systems,such as chip multiprocessors(CMP)and multiprocessor system-on-chips(MPSoC).Similar to most VLSI designs,power-efficiency has also been one of the critical constraints in current NoC design.Usually,the overall NoC power-consumption consists of dynamic switching power and static leakage power.The dynamic power is consumed when the packets are transferred on network and clock circuits switch periodically.However,there is significant consumption of leakage power even without any packet transfers as long as the on-chip resources are power-on.As the technology is continually scaling down and the working frequency is increasing,the leakage power has already become a major portion of power dissipation in NoC design,and its proportion will further increase.In the practical application of many-core system,the throughput demand of NoC may be quite low in most of execution time,and rarely reaches the peak/saturation point.Hence,there are many opportunities in which most routers and links keep in idleness,and this feature can be utilized to solve the leakage power crisis faced by NoC.As a representative low-power technique,power-gating has been applied to current NoC design for alleviating the increasing leakage power.For the static leakage power issues of NoC,this dissertation mainly investigates how to optimize the on-chip router micro-architectures and the power-gating schemes,in order to guarantee the on-chip communication performance while decreasing total power-consumption.The main contributions of this dissertation are as follows.(1)Low-Cost and Low-Power Optimizing Design for Unidirectional Torus NoCThe challenge for NoC design is reducing design complexity to save both area and power while providing high communication performance,such as low latency and high throughput.Especially,with the increase of network size,both design complexity and power-consumption will become the bottlenecks that prevent the network scaling.In this paper,we propose a low-cost and low-power router architecture for the unidirectional torus network;and adopt an improved corner buffer structure for the inoffensive powergating,which has minimal impact on network performance.Meanwhile,an explicit starvation avoidance mechanism is introduced to guarantee the injection fairness of network nodes while decreasing its negative impact on network throughput.The simulation results with synthetic traffic show that our design can improve network throughput by 11.3%on average and achieve significant power-saving in low and medium load region.In the SPLASH-2 trace workload simulation,our design can averagely save 27.2% of total power compared to the baseline,and decrease 42.8% average latency compared to the baseline with corner buffer power-gating.(2)Fine-Grained Power-Gating Optimization of NoC based-on Multi Virtual Channels' Adaptive ManagementIn the power-gating design for NoC,the conventional fine-grained router gating methods will severely decrease network performance due to the continuous cumulation wake-up latency and the head-of-line blocking.Therefore,we propose a multi virtual channels' adaptive management mechanism for fine-grained power-gating to achieve high throughput and low-power,and optimize the wake-up control which is based on the lookahead routing computation.For the synthetic workload simulation,our design can improve NoC performance effectively in medium and high network loads,and respectively increases the saturation throughput by 15.7%?44.1% for different synthetic loads when compared with the conventional optimized design,while keeps power consumption as low as each power-gating design.In the simulation of the PARSEC application trace based-on token protocol,our design can significantly decrease packet's average latency by 20.3% when compared with the conventional optimized method,and only increases less than 3.6% peak power.(3)Power-Gating Optimization of NoC based-on Bit-SlicingIn the conventional power-gating design for NoC,when some gated resources have been in the sleep state,the temporary disconnection of routing channels between some nodes may arise.If the sleeping resources are not activated timely,the temporary disconnection may lead to a significant performance loss on network communication.Hence,we propose a novel partial resource power-gating approach based-on the asymmetrical bitslicing to avoid the performance loss caused by the channels' temporary disconnection.Owing to the slicing of router datapath,we redefine the packet format for the packet's slicing and transferring,and present two essential conversion modules to achieve packet's slicing and reassembling.In the synthetic traffic simulation,our design gains considerable power-saving at low-load,and exhibits better performance behavior than the conventional power-gating design.The application trace simulation shows that our design can averagely save 27.5% of total power compared with the baseline design,and reduce 45.0% packet latency on average when compared with the conventional power-gating design.(4)Power-Gating Optimization of NoC based-on Channel-Direction-SlicingFor the routing channels' temporary disconnection faced by the power-gated NoC design,we investigate the partial resource power-gating approach from another new perspective,and propose the network slicing method based-on the channel-direction-slicing to achieve full connectivity of all on-chip nodes.In the sliced networks of Mesh and Torus topology,we improve corresponding routing algorithms to support packet routing with shortest path,and propose a novel deadlock recovery mechanism to solve possible deadlock situation.Furthermore,clock-gating is applied to the gated router slice to further decrease power.In the synthetic traffic simulation,our designs achieve better power-efficiency at low-load,and show better performance behavior than the conventional power-gated designs.A bit of additional latency may be incurred at low-load,whereas it is more acceptable than the continuous cumulative wake-up delay.For the application trace simulation,our designs averagely consume 15.2%/18.9% more power for Mesh/Torus sliced network,whereas they can averagely obtain 45.0%/28.7% performance improvement when compared with the conventional power-gated designs.