Key Design Technologys Of High Speed Three-Dimensional Integrited Circuits Based On Through-Silicon-Vias

Along with the advance of semiconductor process technology such as lithography,the feature size of devices also presents scaling tendency,resulting in the rapid improvements of the integration and performance of integrated circuit.However,with the feature size of semiconductor devices scaling to the nanometer level,the improvements of integrated circuit performance are gradually slower,and the development of the semiconductor industry is facing increasingly severe challenges.At the same time,due to the restriction of various factors,such as technical level,process cost,physical limits,interconnection delay,and so on,Moore's law which has been leading the development of integrated circuit will face failure.Based on through-silicon via(TSV),the three-dimensional(3D)integration technology can realize the vertical short and dense signal interconnection between layers by TSV,hence has the advantages of good technology compatibility,low cost,few parasitics.And it can integrate heterogeneous function modules,such as analog,radio frequency,logic circuit,and so on.Therefore,it is recognized as a forceful guarantee to sustain Moore's law.In this thesis,the high-speed 3D integrated circuit design technology based on TSV has studied systematically,the main achievements obtained are as follows.1.A method for reducing keep-out zone(KOZ)is proposed.By emplying finite element method(FEM),the thermal stress induced by single-walled carbon nanotube(SWCNT)-based TSV and copper TSV are investigated and compared.The impact of thermal stress on p MOS and n MOS devices aligned along the [100] and [110] directions is analyzed,and the KOZ is evaluated.It is shown that,the KOZ of SWCNT-based TSV is much smaller than that of Cu TSV,but is not negligible.And it is suggested that,the [100] channel orientation is preferred for p MOS and [110] for n MOS,respectively,in order to minimize the KOZ.2.The TSV metal proportion optimization scheme of annular TSV is proposed.For annular TSV-based 3-D ICs,a greater TSV metal proportion of annular TSV leads to lower temperature but induces larger KOZ.The analytical models of the temperature of annular TSV-based 3-D IC and the KOZ induced by annular TSV are given and verified.Based on the analytical models,the figure of merit(FOM)tradeoff model between temperature and KOZ is proposed to obtain the optimal metal proportion of annular TSV.Then,the effects of total radius,material,and insertion density of annular TSV on FOM and optimal metal proportion are analyzed in detail.It is concluded that,the optimal metal proportion of annular TSV is approximately 0.3 with large ranges of the total radius and density of annular TSV,and various materials filled in annular TSV.3.An effective method is proposed to reduce the TSV-induced substrate noise by adding a p+ layer surrounding TSV.The peak noises induced by TSV with p+ layer are compared with those of without p+ layer.And the impact of noise on threshold voltage and saturation current of n MOS are also studied.It is concluded that,the peak noise induced by TSV with p+ layer is reduced by more than 91.8% compared with that of conventional TSV;the transmission parameter is decreased by 21~43 d B after the p+ layer is added;for the case with p+ layer,there are hardly any disturbance to threshold voltage and saturation current of surrounding devices.4.A rigorous inductance model of the solenoid inductor is modeled by analytical method using the concept of loop and partial inductance.Furthermore,the proposed model is validated by the Q3 D extractor and measurement.With this model,the inductance can be estimated accurately with different turn numbers,TSV heights,spaces,and pitches.As the advantages over other methods to derive the inductance value of TSV-solenoid inductor,the proposed model is high in accuracy,fast in simulation speed,high in processing efficiency,convenient in change design parameters,and intuitive for parametric analysis in 3D IC design.5.The design methods of RF/microwave integrated circuits based on the TSV are proposed.The operating performance of RF/microwave frequencies and parasitic parameters of TSV is studied,and the equivalent circuit model and the 3D finite element model is established and validated.On this basis,a novel 3D lumped RF low-pass filter based on TSV and the corresponding equivalent circuit model are proposed.By combining SPICE simulation and Hspice simulation,the proposed filter is verified.