Research On High Energy Efficiency Of Timing Error Tolerant Technique For Embedded Wide-voltage Processor

For now,low-power technique is still an ongoing topic of research to maximize system lifetime.And near-threshold computing becomes one of the mainstream methods to solve this problem.However,if circuits work in the near-and sub-threshold voltage,PVT variations have a big negative influence on the stability of system performance.The traditional design employs large design margins to make the circuit work right,which leads to a large area,power and performance overhead.In order to solve this problem,researchers propose timing error resilient technique.Without adding the design margins,the system uses the online timing error detection and correction circuits to protect the system from PVT variations.This paper focuses on the error resilient technique and studies the light-weight timing error detection and correction mechanism for embedded commercial processor in wide-voltage operation.The contribution and contents are as follows:1.Timing error prediction mechanism based on instructions' execution characteristic.By studying the influence of instruction execution on the critical path of processor combined with the timing error information through running the test cases,a timing error prediction technique based on the instruction execution characteristic is proposed.It monitors the processor state by watching the instruction type and operand and predicts whether the processor will face a timing violation at current cycle.If the timing error signal flags,the system will perform the timing borrow operation for the register locating at the end of the critical path.In this way,it can have more time to perform the calculation and the timing error can be avoided.This method combines the prediction methodology in system level with error correction technique in circuit level and achieves a low hardware cost to realize the timing error prediction mechanism.At the same time,it introduces the timing borrow technique for register-based design.So it can lower the system error rate and improve the performance with an improvement of 18%in energy efficiency.2.Timing error resilient clock gate design for wide-voltage application.Through studying the critical wall phenomenon of clock gate in error resilient system and analyzing the requirement of different clock gating techniques on clock gate implementation,two kinds of timing error resilient clock gates for wide-voltage application are proposed.When the error resilient system introduces clock gating technique to reduce clock tree power,the clock network may have timing violations.And the critical wall of clock gate has been analyzed,which indicates that it needs to add timing error detection and correction mechanism for clock gate.This method uses the inner node to monitor the voltage change and get the timing error information correctly.And the cells have the ability of self-correction and generate the useful output.In this way,once the clock gate in the critical path faces a timing violation,it can still generate the effective clock signals without flushing the pipeline and replaying the error instruction.Moreover,the timing constraints analysis of the error resilient clock gate is different from the register'.This paper shows the detailed implementation method of error resilient clock gate and its corresponding timing closure analysis in wide-voltage operation.It proposes two kinds of error resilient clock gates and targets at the light-weight application and wide-voltage universal system in order to solve the timing error in clock network.And the working mechanism of each cell with different clock gating technique is also given.These two proposed error resilient clock gates add only four and twelve transistors compared with the traditional one.And the final results show that the energy efficiency of error resilient design is 166 GOPS/W in near-threshold voltage and improves by 68%compared with the baseline design.3.Self-gated timing error resilient cluster of sequential cells.By researching the clock gating technique and timing error detection and correction mechanism,it combines the clock gating method and error resilient circuits and uses the same hardware to realize two kinds of function in different period of the same clock cycle.This method can help reduce the timing error detection cost of each critical register and provide the ability of clock network shutdown to reduce the dynamic power of clock tree.Moreover,it proposes a clock self-gated timing error resilient cluster which includes two kinds of sampling cells.The cluster can work in the wide-voltage application and sample the critical data with the ability of self-correction when timing violation of any cell occurs.Moreover,it introduces a timing error resilient clock gate with only two transistors added.In this way,it can reduce the hardware cost of timing error resilient circuits based on circuits sharing and improve the system energy efficiency by reducing the clock network power.The cluster only introduces 13 additional transistors and the simulation result shows that the energy efficiency of the proposed design improves by 19.4%compared with the latest EDAC design.The key techniques proposed in this paper have a positive influence and application value on the optimization of hardware cost and energy efficiency for the error resilient system in embedded commercial processor.