Research And Design Of CMOS Monolithic Integrated 3D Hall Magnetic Sensor

In recent years, integrated Hall magnetic sensors have been widely used in industrial automation, instrumentation, automotive, consumer electronics and other fields, due to a few advantages such as high reliability, low cost, low power consumption. At present, an important development trend of Hall integrated sensor is to realize a monolithic integrated three-dimension (3D) Hall magnetic sensor in CMOS technology, which includes one-dimension (ID) horizontal Hall plate, two-dimension (2D) vertical Hall devices, offset and noise elimination circuit, read-out and interface circuit, and digital signal processing circuit on a same silicon substrate. As the integrated 3D Hall magnetic sensor can detect the spatial 3D magnetic field, it will be further used in magnetic-based navigation system for angle measurement, short distance accurate ranging, endovascular interventions, aircraft nondestructive testing, and so on. However, due to high impurity concentration, shallow depth and impurity Gauss distribution of N-well in CMOS process, the magnetic sensitivity of CMOS integrated Hall devices is very low, especially for the vertical Hall devices. At the same time, suffering from mask alignment mismatch, non-uniformity distribution of impurities in active area, and influence of packaging stress etc, the offset voltage of CMOS Hall devices is very high. On the other hand, the spinning current technique has been successfully used in horizontal Hall sensors for elimination of offset and low frequency 1/f noise. However, the two-axis magnetic signals in 2D vertical Hall sensors require same amplification processing operation. Meanwhile, very large offset of vertical Hall device usually leads to improper operation of offset cancellation circuit. Thus, it is difficult to design signal conditioner for 2D vertical Hall sensors. In addition, in order to design and simulate a signal conditioner with Hall offset cancellation and signal amplification functions, an accurate circuit simulation model to evaluate performances of Hall device is requied. However, the existed simulation models have disadvantages such as complex structure, poor versatility and low portability; moreover, it cannot fully consider various physical, process and geometric effects of Hall devices, especially the influence of lateral diffusion and junction field effects for the scaled Hall devices. This thesis addresses these problems in the design and manufacture of CMOS monolithic integrated 3D Hall magnetic sensors. The structure improvement and layout optimization of Hall device, the dynamic offset cancellation technique and the Hall device simulation modeling are investigated in detail. The main research contents and results are summarized as following:(1) Improvement and optimization of CMOS integrated horizontal and vertical Hall devices. A long-contact Hall plate (horizontal Hall device) is applied. As the contact length exceeds the N-well active area, offset voltage from mask alignment mismatch in the manufacturing process is significantly reduced. Through optimization of the finger ratio of cross width to cross length (W/L) and the shape of Hall plate, the voltage related sensitivity and current related sensitivity are improved simultaneously. An implantation method of P-gurd ring and N-well overlapping, including the partial p+ implanting between contacts is used for five-contact vertical Hall device. As a result, N-well impurities concentration is effectively reduced and Gauss distribution of N-well doping concentration is also improved, resulting into the increase of magnetic sensitivity of five-contact vertical device. A partial N-well implantation technique is also investigated. The doping level of N-well is obviously reduced by means of impurity lateral diffusion and compensation effects, which leads to the significant improvement of current related sensitivity. This method provides a solution to the low sensitivity problem for vertical Hall devices in nano CMOS process.(2) Research and establishment of the simulation models for CMOS integrated horizontal and vertical Hall devices. A simplified compact model is presented for cross-like Hall plate. The model is consisted of a passive network, including eight non-linear resistors and four current-controlled voltage sources. A new method combined with device model structure and the Van-der Pauw measurement is proposed to calculate the nonlinear resistors of N-well, which avoids complex JFET modeling. The model not only takes into account non-linear conductivity, geometry dependence of sensitivity and temperature drift effects, but also considers the lateral diffusion and junction field effects. The error between the model simulation and experimental results is less than 10% for the current related sensitivity and input resistor. In addition, a new compact behavioral simulation model for CMOS five-contact vertical Hall devices is also introduced. In term of the internal current flow geometry, the vertical Hall device is modeled with an asymmetric Wheatstone bridge structure. The model consists of four current-controlled Hall voltage sources and four asymmetric lumped resistors. The lumped resistors on the Wheatstone bridge can be calculated preliminarily by conformal mapping method. Further, its voltage-dependence non-linear characteristic due to the lateral diffusion and junction field effects is considered, which improves the model simulation precision. Compared with the tested results, the simulation error of the current related sensitivity and input resistance with bias changing is less than 15%. The two simulation models have been implemented in Verilog-A hardware description language and they can be directly performed on the circuit simulators, such as Cadence Spectre for ciucuit simulation. They show significant advantages of strong universality and practicality.(3) Study of dynamic offset cancellation technique based on spinning current method for integrated Hall sensor. A new two-phase spinning current circuit is proposed. It is composed of eight NMOS switches controlled by a pair of complementary clock and an operational amplifier, which can achieve the common mode voltage stability in 1/2VDD.It also avoids the drift of quiescent working point of the operational amplifier and ensures the operating reliability of the offset cancellation circuit. A novel offset cancellation and signal amplification circuit for 2D vertical Hall sensor is introduced. It applies both 2-phases spinning current modulation technique and correlated double sampling demodulation technique to effectively eliminate Hall offset. In addition, it uses signal multiplexing technique to dispose the input 2D Hall signals on X and Y axis with the same magnification, which avoids the amplification errors between two axis Hall signals and also greatly reduces the power consumption. By using the simple principle of spinning current modulation and sample-hold-addition demodulation, the 1D horizontal Hall sensor also demonstrates the strong ability of eliminating offset and 1/f noise as well.(4) Design and implementation of monolithic integrated 3D Hall magnetic sensor chip. Based on CSMC 0.8 ?m high voltage CMOS process, a linear integrated 3D Hall sensor with in-chip horizontal and vertical Hall devices, offset cancellation circuit and signal amplification circuit, has been devised and fabricated. The chip tested results show that the voltage and current related sensitivity of optimized cross-shaped Hall plate reach 0.034 V/VT at 3 V bias voltage and 250 V/AT at 1 mA bias current, respectively, and the offset voltage is less than 2.5 mV under 3 V bias. The voltage and current related sensitivity of the optimized five-contact vertical device achieves achieve 0.032 V/VT at 3 V biasing and 130 V/AT at 1 mA biasing, respectively, meanwhile less than 4 mV offset voltage is obtained at 3 V bias. Under 5 V supply voltage, the maximum Hall output voltage of 3D Hall sensor microsystem is up to ±2.1 V, and the detectable magnetic field is ranged from 5 mT to 170 mT. The linearity of Hall output voltage is greater than 99%. The equivalent residual offset is less than 1.15 mT and the static power consumption is 42 mW.