Design Of High-voltage IGBT And Reliability Study Of Power Devices

As the latest generation of somposite full-controlled power devices, IGBT has most outstanding characteristics, such as voltage control, large input impedance, small driving power, simple control circuit, low switching losses, and high operating frequency. High-voltage IGBT plays an irreplaceable role in motor control, new energy, rail transportation, smart grid, electric vehicles, and other fields. However, due to relatively late research, technology lags behind, resulting in the design and production of high-voltage IGBT long-term behind foreign countries. The purpose of this thesis is to combine the existing domestic technology, research, and development of high-voltage IGBT with independent intellectual property rights, and accumulate certain experience for domestic high-voltage IGBT design.In addition, the power device’s reliability problem has become one of the key problems affecting the overall ferformance of the power integrated circuit. Through the research of hot carrier degradation and off-state avalanche breakdown degradation of SG-NLDMOS by experiments and simulation, this thesis reveals the degradation mechanisms and put forward the measures of improvement. The research can provide certain reference value for the power device reliability design and evaluation system.The main work and innovations include:1. Put forward the design method of high-voltage IGBT. Design1700V NPT-IGBT, including its cell structure, terminal structure, process, and layout design. The structure of the various parts of cell parameters was determined through analysis the principle of the device and simulation the device. The field limiting ring combined with field plate was adopted as terminal structure, the influence of field plate arranged on the terminal structure was discussed, and the polysilicon field plate setting scheme was put forward. The process of IGBT back collector was explored to optimize it. To simplify the entire process and the whole process was completed with six photolithographies. And finally the layout with gate in the center was designed.2. The structure of N+diffusion remnant layer was proposed to improve the JFET resistance of planar gate IGBT, thus improving the on-state voltage drop at the same time without a significant breakdown voltage decline. The structure of N+diffusion remnant layer was applied to the trench gate IGBT which is proposed DR-IGBT, and compared with conventional NPT-IGBT and LPT CSTBT. Under the same breakdown voltage, the on-state voltage drop and current capability of DR-IGBT are superior to NPT-IGBT. The breaddown voltage of DR-IGBT is higher than LPT CSTBT, while the voltage drop of DR-IGBT in the high current density is lower than the LPT CSTBT. By introduction of P-buffer layer to optimize the back structure of IGBT, the NPN aided fast switching IGBT (NFS-IGBT) is presented, which has visibly better trade-off relationship between on-state voltage drop and turn-off time.3. The NPT-IGBT fabrication used high resistance float zone silicon crystal with neutron transmutation doping as substrate and making of a MPW mask. After the chip completed, the NPT-IGBT was packed with the half-bridge module and tested. Vces>1700V, Ic=100A (125℃) Vth:5.2V, Ige<80nA, Toff=0.744μs, Eoff=25mJ. All the electrical characteristics meet the disgn requirements, except Vces=3.7V.4. The hot carrier effect of SG-NLDMOS was investigated by DC voltage stress, TC AD simulation, and charge pumping test. The hot carrier effect of SG-NLDMOS is associated with the gate voltage. When stressed under middle Vgs, interface states and positive oxide trapped charge generation in the accumulation region under the poly step cause the degradation. When stressed under high Vgs, interface states formation in the spacer region near the drain contact play a leading role. The structural parameter affects on the hot carrier effects have been studied and the measures of improving the hot carrier degradation are put forward. The degradation induced by off-state avalanche breakdown of SG-NLDMOS was investigated by current pulse stress, TCAD simulations, and charge pumping test. The degradation induced by off-state avalanche breakdown is similar to the stacked hot-carrier degradation under high Vgs and middle Vgs. The positive oxide trapped charge generates in the accumulation region, while the interface states have increased in the whole drift region.