Wire Estimation Algorithm In Physical Synthesis

Logic synthesis is the milestone of the modern digital chip design. The synthesis tools take the circuit design from the schematic era into the logic description era. Two critical factors make the synthesis tools succeed, the first is the embedded, increased, static timing analyze engine, the second is the timing driven synthesis engine, which including choosing the logic circuit structure in the technology independent stage and choosing the logic cells in the technology dependent stage. The embedded timing engine must correctly deal with the cell delay model; interconnect delay model and constraint management. The good timing analyze result is dependent on the accurate timing model, the parasitic parameter model and the analysis computer engine. The wire load model which based on the lookup table, can give out the cell delay and wire delay according the fan in, fan out and drive length of the logic cells. The wire delay of the CMOS technology whose feature size above 0.25μm is relative small to the total delay, we can get the logic cells delay and the wire delay according the wire load model from the Fab, then estimate the total delay and area and choose the suitable circuit implement from the design space for the design engineers.In the DSM design, especially below the 0.13μm,the original ignored second effect must be considered in the DSM design, otherwise, we can not get the correct delay and area of the circuit. In the DSM design, the wire load model of the traditional synthesis can not correctly and precise estimate the delay of the path in the design. The traditional synthesis tools succeed is because of the high quality timing engine, which can compute the delay and area of the different implement style of the same logic function and help the synthesis engine to choose the most suitable circuit, deal with the timing borrow, register retiming, logic duplication, etc for the design engineers. But in the DSM design, the wire delay exceed the logic delay and the area of the wire also exceed the area of the logic cell, the old timing analyzing engine and synthesis engine can not get the corrected delay and then can not choose the suitable circuit from the circuit logic description. The synthesis process must be changed from the logic cell centre method to the wire centre method in order to deal with the DSM design, the different logic cell choose is the method to implement the different interconnection structure. We estimate the cell placement and wire delay in real time when execute the synthesis according characterize of the DSM design to direct the circuit synthesis. This method estimates the wire resource according the aggregate impact of the grids which contain the logic cells and wires. The company algorithm does not affected by the current placement algorithms, which used to estimate the wire resource, congestion in the synthesis stage, and keep the consistent result with the industry placement algorithm and void the complex, heuristic, time-consuming process, and quickly gets the result. The synthesis tools can quickly get the feedback result from this algorithm and use it to choose the most suitable circuit from the design search space for the designers. The congestion coefficient is gotten from the GBWE algorithm. With the controllable localized cells placement process and the controllable congestion spread algorithm, we can get the stable, precise congestion coefficient and prohibit some uncertain factor in the traditional heuristic algorithms. The congestion coefficient can delegate the routable of the corresponding modules. According the statistical result, we can get the relation between the congestion and the ratio of the wire length and the distance of cells under specific technology, and then get the path delay from the model by static timing analysis engine. The delay and area can be used to direct the circuit synthesis process.This paper presents the process of the GBWE algorithm and it's application in the synthesis process, and give out the experiment comparing results with traditional iterative methods.