Study Of A Multi-threaded Network Processor With Distributed Micro-architecture

With the rapid increment of data transferring capability in network medium and the ever-changing and more and more complex networking applications, a new kind of RISC processor called Network Processor (NP) is emerging to cope with the challenging requirement. With the merits of high performance and programmable character, NP is considered as a key technology that promotes the development of next generation network.In order to meet the line-speed processing capability for backbone network nodes, it is a critical problem that how to improve the performance of NP. And then it has posed a challenge to network processor architecture designers.Supported by the National Defense Preliminary Research Project and the 863 Research Plan of China, the author takes part in the research of "LongTeng" series System On Chips, and studies in-depth the high performance network processor architecture. The main contributions in this dissertation are given below.1) The network protocol processing engine for "LongTeng"Sl and "LongTeng"S2 has been designed based on the research of a novel multi-threading micro-architecture. The "LongTeng"S 1 has been implemented by 0.18μm CMOS technique successfully. The transistor count is 4 millions. The "LongTeng"Sl has passed the test in the real application system. Till now, the architecture design of the "LongTeng"S2 has been finished as well.2) A novel Thread Level Distributed Processing (TLDP) architecture for high performance network protocol processing is proposed, to cope with the conflict between performance requirement and programmability. It is a dynamic multi-threaded Multi-core architecture from the hardware designer's view, while the inner parallel mechanism is transparent to system programmer. It is convenient for programming and implementing real time load balance in TLDP architecture.3) In the research of a 32 bits multi-threaded packet processing micro-engine, a dynamic threads scheduling scheme is presented by a BGCG (balanced in group and cyclic among groups) multi-threading mechanism. Under this kind of dynamic thread scheduling scheme, zero overhead of context switching mechanism and free of instruction pipeline stall are implemented naturally. The maximum packet forward rate for IPV4 and IPV6 is 1785 and 1587 kpps respectively.4) A novel high performance routing table lookup and update algorithm based on index and indirect compressing scheme is presented in the research of fast IP address lookup. Not only one SRAM access cycle routing table lookup performance is accomplished, but two SRAM access cycles update performance is achieved when implemented in a pipelined scheme. According to the all-around performance, such as search and update performance, cost and consuming power, this work is better than the Gupta's DIR of standford and Degermark's SFT solutions. It is benefit for resolving the latency uncertainty when routing table lookup engine is accessed and simplifying the synchronization mechanism under the distributed processing architecture.5) A kind of threads dispatching and scheduling mechanism with dynamic adaptive load...