Resource Scheduling For Network Processors

Increasing requirements of network rates and sophisticated networking services make the traditional networking devices based on GPP or ASIC a bottleneck of networking applications. As a solution, Network Processor (NP), which has high processing rate and flexible programming ability, is adopted in the design of networking application systems more and more widely.NP generally consists of multiple parallel real-time processing RISCs, called Processing Engines (PEs), each of which supports multiple threads. PEs are responsible for packet processing, networking bandwidth managing, and so on. A focus of attention is how to allocate and schedule resources effectively to improve system throughput, reduce packet delay and developing time, ensure system requirement of Quality of Service (QoS).This paper is based on the project "Network Processor Architecture Faced New-type Operating System Core Technique" sponsored by the National High-tech Development Plan (863 plan). Two problems are addressed in the paper:. A problem that must be faced when designing systems based on NPs is how to assign the packet-processing tasks to the processor pipelines consisting of many processing engines. Nowadays, this work is done manually, which is error-prone and inefficient. To alleviate this, this paper proposes a genetic algorithm-based method to assign processing tasks to processing engines automatically.. This paper then addresses the problem of QoS scheduling of processing resources on NP. We first present a packet scheduling algorithm SFQ+ based on SFQ and DWCS, which improves the fairness sharing of bandwidth. As network processing workloads are highly regular and predictable, we present a processor scheduling algorithm called Forecasting-based Fair Queuing (FFQ) which uses these estimates and provides significantly better delay guarantees than processor scheduling algorithms which do not take packet execution times into consideration.Researches are based on the hardware architecture of Intel IXP2400. Experiments of this paper are based on the evaluation board, ENP-2611, a product of RADISYS Corporation. Software is Linux GNU tool chains for XScale and Intel Workbench.