Study Of High-performance Computer Storage

With the rapid development in semiconductor technology, the disparity of data access cycle-time between the fast microprocessors and the relatively slow main memory systems become more and more serious. The computer designers use the parallel memory system and hierarchical memory systems in their computers in order to reduce the average access time of the memory system.However, practical experiences have shown that the traditional interleaved parallel memory system architecture and hierarchical memory systems can not satisfy well the most frequently used data accesses in a wide variety of application algorithms. This is because the most frequently used data patterns can produce many memory bank conflicts in the traditional parallel memory system or cache memory line conflicts in the cache memory systems. Address mapping methods used in the parallel systems or the cache memory systems have important effects on the conflict rates.XOR schemes are a set of nonlinear skewed memory allocation schemes which can be used in the parallel memory systems. We present a XOR scheme, named LR-XOR scheme, after careful studying the former schemes. In a parallel memory system with N=2~i memory banks, the processing units can access most of the data patterns frequently used in scientific and engineering programs only in one memory access cycle. These include the row, column, main PxQ block, scattered PxQ block, main vector and shifted main vector with 2~i stride of NxN matrix. These parallel access properties can reduce the memory system's average data access time.Comparing the behavior of parallel memory system and the behavior of the cache memory system, we found that the memory schemes used in parallel memory system should have good properties if they are used as cache memory mapping schemes. Our theoretical analysis stated that if we use the EE-XOR or...