Design And Implementation Of Multi-core Processor Memory System For The Future Oriented Communication Algorithm

Spectrum resource has become a heavily effect on the development of wireless communication. How to effectively improve the utilization of limited spectrum resource in wireless communication becomes a key issue for future wireless communication technology. As DPC(Dirty Paper Coding) is better to achieve the wireless communication system capacity limit, it has become a key technology for future communication. DPC algorithm is typical computing intensive application, and has strong data parallel feature. Its basic operation is able to meet the producer-consumer model. Processor is the core of researching communication algorithms. Most researches on multi-core processor are designed for a wide range of application areas such as the desktop and high performance server, so they are unable to meet the demand of communication algorithms for processor platform. Multi-core processor of the future oriented communication algorithm is high performance new processor special designed for communication algorithms study. The processor can support simultaneous multi-threading(SMT) and single instruction multiple data(SIMD); can effectively realize the function and performance of DPC algorithm. The research results have great theoretical and practical significance for the development of the next generation of wireless communication technology. Based on thorough study of DPC algorithm and the multi-core processor architecture, this paper proposed a new parallel architecture, and conducted research on the key technology of CMP.Based on thorough study of the DPC algorithm on access demand characteristics and related design of multi-core processors memory system, this paper bears part design work of multi-core processor memory system on future oriented communication algorithm. This paper designed a multilevel memory structure which shares two-level memory. In order to extend the physical address space, this paper designed the separate data memory management unit(MMU). The design of this paper realizes L1-Cache structure. There is data locality in irregular access out of the frequent access to data space of DPC algorithm, data processing is in accordance with the producer-consumer model. Because DPC algorithm not only need traditional Cache as on-chip shared Cache, but also need scratchpad memory(SPM) as multiple access feature of on-chip shared memory, so this paper designed a shared memory structure of L2-Cache/SPM hybrid to effectively reduce access latency and to improve the performance of CMP memory system.This paper completed the RTL description with the use of Verilog HDL part design on memory system, completed RTL simulation of memory system based on VCS software simulator platform, which ensured the correctness of the design. In the end, this paper conducted the logic comprehensive optimization with the use of Design Complier logic synthesis tools in the 90 nm Process Library.