Research On High Speed Networks Of Shared Virtual Memory Clusters

Nowadays the networks of clusters are either costly or feeble for shared virtual memory. This dissertation tries to design a custom high-performance cluster network named FRAMP (Fast Remote Access and Message Passing). It would not only provide fast message passing and give hardware supports for shared virtual memory, including RDMA and automatic TLB updates, but also remain at a low price.The current and trend of parallel computing and interconnection networks are discussed in this dissertation. It is shown through the test of benchmarks that how a variety of communication patterns affect the performance of parallel computing and the requirement of cluster interconnection is to use high speed networks and simple communication protocols. An improved cut-through switching is put forward in this dissertation, which is called exhausted cut-through. It cut through packets like virtual cut-through switching method when no conflicts. When blocking, it first buffers packets as more as possible and then holds the links as wormhole switching does. It requires no additional hardware, but improves link availability.The FRAMP network uses exhausted cut-through switching, slack flow controlling, source-based routing and synchronous data transfer. A custom light-weight communication protocol is designed. The main idea is that user processes direct access network interface, data copies and interrupts are reduced, the network layer and link one are incorporated, and the useless pattern in the packets is discarded.The prototype of FRAMP switch is a 4×4 FPGA-based fast switch, which adopts an input-queued distributed-scheduling crossbar as main switching structure. It uses dual-clock synchronized FIFOs as packet buffers, which isolate output clocks from input clocks. FRAMP switch adopts slack flow control based on the status of FIFOs, which improves link availability and increases transmission rate. The FRAMP switch adopts an improved cut-through switching method and transfers data and controls synchronously, which pipeline packet transfer and reduce transmission delay. In order to reduce scheduling delay, the FRAMP switch uses distributed arbiters to schedule packets. For further improvement, it takes only one clock cycle to complete one modified Round-Robin scheduling with initial value. It reduces switching delay and impoves switching efficiency, but remains low hardware cost. The FRAMP network supports four data transfers: small message sending and receiving, big message sending and receiving, RDMA (Remote Direct Memory Access) read and RDMA write. The main parts of the FRAMP NIC (network interface card) are a powerful FPGA chip, some interface controllers and buffers. The FPGA performs most logic functions of NIC: local bus scheduling, fast sending and receiving of small or big messages, searching and updating...