.32-bit Embedded Cpu's Ultra-deep Sub-micron Physical Implementation And Verification

IC industry has entered the nanometer-scale SOC era. With feature size scaling down, new process technology brings new challenges to the design methodology. New problems are encountered in functional design, simulation, formal verification, testing and other fields. In physical implementation domain, brand-new challenges represented by wire-delay are encountered because of smaller feature size.In this paper, a flow of physical implementation and verification of VDSM IC is presented. New challenges introduced by new process in this domain are analyzed. An advanced physical implementation and verification flow for 0.18 technology, which is based on new characteristics of VDSM process, is built. A 32bit embedded CPU - CK510 has been implemented following this flow.To overcome the drawbacks in existing IR-drop analyzing methods, a novel algorithm with maximal voltage-drop finding ability is presented. For migration of CK510 to new process, a DFM-friendly 90nm standard cell library is designed.Main contributions in this thesis are:1. A detailed VDSM physical implementation flow is presented, with some new technologies such as physical synthesis, silicon virtual prototyping and IR-drop verification being discussed in detail.2. CK510's physical implementation guideline is presented based on CK510's spec and new characteristics of 0.18um process.3. A full chip flatten physical synthesis design flow is presented. This flow has short turn-around time and better timing performance than traditional flow. Based on this flow, CK510 is implementedboth in TSMC and SMIC 0.18um process. The tapeout results show that design spec is reached.4. A novel GA based algorithm for UDSM VLSI power grid verification is presented. Unlike other existing techniques, this algorithm possesses merits of both the static and dynamic IR-drop analysis methods. For large scale combinational circuits, the maximum IR-drop can be automatically found following the proposed scheme, so local deep voltage drop which can't be seen by static method can be found by this new method, and no input vectors are needed.5. DFM (Design for Manufacturability) method of nanometer scale standard cells is analyzed. A new DFM implementation and verification design methodology is presented, with includes a group of technologies for process modeling, test circuit structure and DFM problem location. A set of DFM-friendly 90nm standard cells are designed with this methodology.New physical implementation flow of processes below 0.18um is planned to be researched. The 90nm standard cell library will be improved according to real testing results of the designed 90nm library.