The Design And Implementation Of The40nm Manufacturable Standard Cell Library

Currently, the top-down methodology is adopted by most system design andstandard cell library has played an important role in the design method. When thesemiconductor industry has entered into the nanometer era, the physicalimplementation of the standard cell must not only consider the timing, power andarea, but also consider the yield decline due to the silicon surface distortion causedby lithography. The issues of manufacturing have to be considered in the designphase. At this time, a new field of research named design for manufacturability(DFM) has generated. Standard cell library is the bridge between process anddesigner, so we must consider the manufacture for standardcell library.This paper proposes a design method for40nm DFM standard cell librarywhich optimizes the library design flow and design project and can make the processof OPC more convenient. To achieve this goal, this paper constructs a40nm DFMstandard cell library according to the design rule supplied by the foundry, the designflow, and the requirements of the performance. Combining with DRC rule and DFMrule to instruct designing of layout at the stage of designing layout. The factor ofmanufacture to be considered integrated into the design phase to solve the possibleproblems of the late stage as soon as possible and avoid the structure of layout whichwill cause hotspot effectively. Using RET amendment to the standard cells andoptical simulation technology to optimize the cell structure in favor of theimplementation of the OPC technology and greatly improve the manufacturability ofthe cell library. Extracting the parasitic from the optimized layout and establishingthe complete model of cell library so as to support IC design flow, include: symbollibrary, simulation library, synthesis library and PN library model. Finally, verifyingthe40nm DFM standard cell library.The DFM standard cell library not only meet the requirements in terms offunctionality, timing, area and power, it passes the foundry TD’s manufacturabilitytest which prove the standard cell library has strong manufacturability and makes forthe yield of40nm process improvement. Through the comparative analysis oftapeout test results, synthesis library and HSPICE simulation results, this paperproposes the recommendations of the digital circuit design.