Research On The Design Optimization Techniques For System-On-Chip Testing

This dissertation describes the investigation on some algorithms and realization design optimization techniques for SOC (system-on-chip) test. Research directions mainly include BIST optimal design under power constrains, SOC test structure optimization and high-level DFT optimization. The motivation of this dissertation is to find simple and effective algorithms and suitable related test architectures, so as to optimize the test application of SOCs. The contributions of this dissertation are as follow:Because of using the embedded core based SOC design method and considering the need of keeping secretly, the inner structures of cores are usually unknown. The test of cores can be handled by using BIST technology. With embedded test drivers and test response analyzers, the test can be finished in the cores.The random pattern BIST has the characteristic of simple structure, easy implementation. But its test pattern usually very long and it is hard to reach a satisfy test coverage for some random resistance faults. At the same time, the length of random test pattern and its correlation lead to states change frequently during the test. Therefore, it consumes more test power and has an ill influence on the safety of SOCs. Then a weighted random pattern generator and test scheduling algorithm were introduced here to overcome above shortcomings. With multi-weighted sets, the BIST can decrease the test length and increase test coverage to random resistance faults. Also with the test scheduling algorithm between weights can optimize the test pattern correlation and lower test power consume.After that, a new multi-phase-clock BIST scheduling algorithm was proposed. With a multi-phase-clock and power constrains, several BISTs can be arranged into different test phase and the total test time was decreased. Here, a genetic algorithm was introduced to optimize the test procedure.Using IEEE P1500 and similar CTW (core test wrapper) designs, test control mechanisms and corresponding TAM (test access mechanism) constructed SOC test architecture becomes more and more popular. Under this kind of test architectures, a good test resource distribution and test scheduling strategy will lead to a higher test efficiency. Test bus based test architecture has a problem that how to distribute the test bus among the IP cores. For an optimal test time result, one must distribute the test busreasonable and combine the TAM and CTW design in a whole, then use the efficient scheduling algorithm testing all cores under test resource and test power constrains.Therefore, the dissertation presents a modified TAM and CTW co-optimal design algorithm for SOCs with P1500 test architecture. With a limited SOC test 10 port number, it computed the test efficient factor in test distribute procedure to select a optimal CTW and test bus connection method with a minimal test time, and then schedule the test procedure under test power constraints so that optimizing the test time overall.Furthermore, a multi-objection optimal algorithm based test architecture design algorithm was proposed. It treated the test resources and constrains as objections to be optimized concurrently. As a result, the test resources were allocated reasonable and finally test power as well as test time were optimized.The SOC design method has moved to higher level now. Such as system level, behavioral level and RTL (register transform level) design becomes more popular. The high level design for testability has the merits that the tests can be divided in the system level, the test generator and test structures can be optimized in module perspective, and the repetition of the test design procedure between high level and gate level can be reduced greatly. A RTL BIST test structure optimal method was developed by analyzed the functional HDL description designs. This BIST design in high level had the less test cost over the gate level BIST insertion. Also, the system level DFT was discussed primarily after that.Finally, combining with a self-design computer vision SOC architecture, a DFT structur...